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    INTEGRATED CIRCUIT DEVICE INCLUDING THROUGH-SILICON VIA STRUCTURE HAVING OFFSET INTERFACE
    6.
    发明申请
    INTEGRATED CIRCUIT DEVICE INCLUDING THROUGH-SILICON VIA STRUCTURE HAVING OFFSET INTERFACE 有权
    集成电路设备，通过具有偏移接口的结构，包括硅

    公开(公告)号：US20130119547A1

    公开(公告)日：2013-05-16

    申请号：US13603978

    申请日：2012-09-05

    申请人： Su-kyoung Kim ,  Gil-heyun Choi ,  Byung-Iyul Park ,  Kwang-jin Moon ,  Kun-sang Park ,  Dong-chan Lim ,  Do-sun Lee

    发明人： Su-kyoung Kim ,  Gil-heyun Choi ,  Byung-Iyul Park ,  Kwang-jin Moon ,  Kun-sang Park ,  Dong-chan Lim ,  Do-sun Lee

    IPC分类号： H01L23/532 ,  H01L23/498

    CPC分类号： H01L21/76898 ,  H01L23/481 ,  H01L23/49827 ,  H01L25/0657 ,  H01L2224/16 ,  H01L2924/13091 ,  H01L2924/00

    摘要： An integrated circuit device includes a substrate through which a first through-hole extends, and an interlayer insulating film on the substrate, the interlayer insulating film having a second through-hole communicating with the first through-hole. A Through-Silicon Via (TSV) structure is provided in the first through-hole and the second through-hole. The TSV structure extends to pass through the substrate and the interlayer insulating film. The TSV structure comprises a first through-electrode portion having a top surface located in the first through-hole, and a second through-electrode portion having a bottom surface contacting with the top surface of the first through-electrode portion and extending from the bottom surface to at least the second through-hole. Related fabrication methods are also described.

    摘要翻译： 集成电路器件包括：第一通孔延伸穿过的衬底和衬底上的层间绝缘膜，所述层间绝缘膜具有与第一通孔连通的第二通孔。 在第一通孔和第二通孔中设置有硅通孔（TSV）结构。 TSV结构延伸穿过衬底和层间绝缘膜。 TSV结构包括具有位于第一通孔中的顶表面的第一通电极部分和具有与第一贯穿电极部分的顶表面接触并从底部延伸的底表面的第二通电极部分 表面至少到第二通孔。 还描述了相关的制造方法。

    Methods of fabricating integrated circuit capacitors using a dry etching process
    10.
    发明授权
    Methods of fabricating integrated circuit capacitors using a dry etching process 失效
    使用干蚀刻工艺制造集成电路电容器的方法

    公开(公告)号：US07547607B2

    公开(公告)日：2009-06-16

    申请号：US11176519

    申请日：2005-07-07

    申请人： Kwang-jin Moon ,  Gil-Heyun Choi ,  Sang-Woo Lee ,  Jae-Hwa Park

    发明人： Kwang-jin Moon ,  Gil-Heyun Choi ,  Sang-Woo Lee ,  Jae-Hwa Park

    IPC分类号： H01L21/20

    CPC分类号： H01L21/76889 ,  H01L21/28518 ,  H01L21/32137 ,  H01L27/10852 ,  H01L28/91 ,  H01L28/92

    摘要： A method of fabricating an integrated circuit capacitor includes forming a first metal layer on a conductive plug in an interlayer insulating layer on a substrate. At least a portion of the first metal layer is silicided to form a metal silicide layer and a remaining first metal layer on the conductive plug. The remaining first metal layer is removed using a dry etching process. A lower electrode including a second metal layer is then formed on the metal silicide layer. Because the remaining first metal layer is removed, etching and/or other damage to the conductive plug and/or the interlayer insulating layer during a subsequent wet ethching process may be reduced and/or prevented.

    摘要翻译： 制造集成电路电容器的方法包括在基板上的层间绝缘层中的导电插塞上形成第一金属层。 第一金属层的至少一部分被硅化以在导电插塞上形成金属硅化物层和剩余的第一金属层。 使用干蚀刻工艺除去剩余的第一金属层。 然后在金属硅化物层上形成包括第二金属层的下电极。 因为剩余的第一金属层被去除，所以可以减少和/或阻止在随后的湿式加工过程中对导电塞和/或层间绝缘层的蚀刻和/或其它损坏。