公开(公告)号：US06461977B1

公开(公告)日：2002-10-08

申请号：US09417086

申请日：1999-10-13

申请人： Hiroshi Matsuo ,  Takuji Oda ,  Yuichi Yokoyama ,  Kiyoshi Maeda ,  Shinya Inoue ,  Yuji Yamamoto

发明人： Hiroshi Matsuo ,  Takuji Oda ,  Yuichi Yokoyama ,  Kiyoshi Maeda ,  Shinya Inoue ,  Yuji Yamamoto

IPC分类号： H01L21302

CPC分类号： H01L21/67069 ,  H01L21/31116 ,  H01L21/76897

摘要： An improved etching method allowing the formation of a silicon nitride film with an adequate film thickness at the sidewall portion of a pattern is disclosed. A silicon nitride film formed to cover a stepped pattern is dry-etched, employing plasma of mixed gases containing CH2F2 and O2. As a result, a sidewall spacer of the silicon nitride film is formed at the sidewall of the pattern in a self-aligned manner.

摘要翻译： 公开了一种改进的蚀刻方法，其允许在图案的侧壁部分处形成具有适当膜厚度的氮化硅膜。 用包含CH 2 F 2和O 2的混合气体的等离子体干蚀刻形成为覆盖阶梯图案的氮化硅膜。 结果，氮化硅膜的侧壁间隔物以自对准的方式形成在图案的侧壁处。

公开(公告)号：US06444515B2

公开(公告)日：2002-09-03

申请号：US09761176

申请日：2001-01-18

申请人： Hiroshi Matsuo ,  Yuichi Yokoyama ,  Takuji Oda ,  Kiyoshi Maeda ,  Shinya Inoue ,  Yuji Yamamoto

发明人： Hiroshi Matsuo ,  Yuichi Yokoyama ,  Takuji Oda ,  Kiyoshi Maeda ,  Shinya Inoue ,  Yuji Yamamoto

IPC分类号： H01L218238

CPC分类号： H01L27/10873 ,  H01L21/76805 ,  H01L21/76897 ,  H01L23/485 ,  H01L27/10888 ,  H01L27/10894 ,  H01L2924/0002 ,  H01L2924/00

摘要： A hard mask insulating layer is formed on a gate electrode which is formed on a main surface of a silicon substrate with a gate insulating layer interposed. An SiN sidewall spacer is directly formed on a thin SiO2 layer which is formed to cover a side surface of the gate electrode. A contact hole is formed to penetrate an interlayer insulating layer formed on an SiN stopper layer and reach the main surface of the silicon substrate.

摘要翻译： 在栅极电极上形成硬掩模绝缘层，栅电极形成在硅衬底的主表面上，栅极绝缘层被插入。 SiN侧壁间隔物直接形成在形成为覆盖栅电极的侧表面的薄SiO 2层上。 形成接触孔以穿透形成在SiN阻挡层上的层间绝缘层并到达硅衬底的主表面。

公开(公告)号：US5994227A

公开(公告)日：1999-11-30

申请号：US119045

申请日：1998-07-20

申请人： Hiroshi Matsuo ,  Takuji Oda ,  Yuichi Yokoyama ,  Kiyoshi Maeda ,  Shinya Inoue ,  Yuji Yamamoto

发明人： Hiroshi Matsuo ,  Takuji Oda ,  Yuichi Yokoyama ,  Kiyoshi Maeda ,  Shinya Inoue ,  Yuji Yamamoto

IPC分类号： H01L21/28 ,  H01L21/00 ,  H01L21/302 ,  H01L21/3065 ,  H01L21/311 ,  H01L21/60 ,  H01L21/8242 ,  H01L21/8244 ,  H01L27/108 ,  H01L27/11

CPC分类号： H01L21/67069 ,  H01L21/31116 ,  H01L21/76897

摘要： An improved etching method allowing the formation of a silicon nitride film with an adequate film thickness at the sidewall portion of a pattern is disclosed. A silicon nitride film formed to cover a stepped pattern is dry-etched, employing plasma of mixed gases containing CH.sub.2 F.sub.2 and O.sub.2. As a result, a sidewall spacer of the silicon nitride film is formed at the sidewall of the pattern in a self-aligned manner.

公开(公告)号：US06249015B1

公开(公告)日：2001-06-19

申请号：US09115514

申请日：1998-07-15

申请人： Hiroshi Matsuo ,  Yuichi Yokoyama ,  Takuji Oda ,  Kiyoshi Maeda ,  Shinya Inoue ,  Yuji Yamamoto

发明人： Hiroshi Matsuo ,  Yuichi Yokoyama ,  Takuji Oda ,  Kiyoshi Maeda ,  Shinya Inoue ,  Yuji Yamamoto

IPC分类号： H01L27108

CPC分类号： H01L27/10873 ,  H01L21/76805 ,  H01L21/76897 ,  H01L23/485 ,  H01L27/10888 ,  H01L27/10894 ,  H01L2924/0002 ,  H01L2924/00

摘要： A hard mask insulating layer is formed on a gate electrode which is formed on a main surface of a silicon substrate with a gate insulating layer interposed. An SiN sidewall spacer is directly formed on a thin SiO2 layer which is formed to cover a side surface of the gate electrode. A contact hole is formed to penetrate an interlayer insulating layer formed on an SiN stopper layer and reach the main surface of the silicon substrate.

公开(公告)号：US5747843A

公开(公告)日：1998-05-05

申请号：US667684

申请日：1996-06-21

申请人： Hiroshi Matsuo ,  Shinya Watanabe ,  Yuichi Yokoyama ,  Shinya Inoue

发明人： Hiroshi Matsuo ,  Shinya Watanabe ,  Yuichi Yokoyama ,  Shinya Inoue

IPC分类号： G11C11/4099 ,  H01L21/8242 ,  H01L27/105 ,  H01L27/108 ,  G11C5/02 ,  G11C13/00

CPC分类号： G11C11/4099 ,  H01L27/105 ,  H01L27/108

摘要： An improved semiconductor memory device in which an electric circuit operates normally is provided. A block of memory cells of a dynamic random access memory is provided on a semiconductor substrate. A dummy storage node is provided near a corner portion of the memory cell block. A dummy cell plate is provided such that it covers the dummy storage node and is electrically insulated from a main cell plate of the DRAM.

摘要翻译： 提供其中电路正常工作的改进的半导体存储器件。 动态随机存取存储器的存储单元块被提供在半导体衬底上。 在存储单元块的角部附近提供虚拟存储节点。 提供虚拟单元板，使得其覆盖虚拟存储节点并且与DRAM的主单元电池电绝缘。

公开(公告)号：US6033971A

公开(公告)日：2000-03-07

申请号：US160379

申请日：1998-09-25

申请人： Kaoru Motonami ,  Shigeru Shiratake ,  Hiroshi Matsuo ,  Yuichi Yokoyama ,  Kenji Morisawa ,  Ritsuko Gotoda ,  Takaaki Murakami ,  Satoshi Hamamoto ,  Kenji Yasumura ,  Yasuyoshi Itoh

发明人： Kaoru Motonami ,  Shigeru Shiratake ,  Hiroshi Matsuo ,  Yuichi Yokoyama ,  Kenji Morisawa ,  Ritsuko Gotoda ,  Takaaki Murakami ,  Satoshi Hamamoto ,  Kenji Yasumura ,  Yasuyoshi Itoh

IPC分类号： H01L21/316 ,  H01L21/76 ,  H01L21/762 ,  H01L21/8234

CPC分类号： H01L21/823475 ,  H01L21/76205 ,  H01L21/7621 ,  H01L21/76216

摘要： There are provided a semiconductor device, which includes an element isolating oxide film having a good upper flatness, and a method of manufacturing the same. Assuming that t.sub.G represents a thickness of a gate electrode layer 6, a height t.sub.U to an upper surface of a thickest portion of element isolating oxide film 4 from an upper surface of a gate insulating film 5 and an acute angle .theta.i defined between the upper surfaces of element isolating oxide film 4 and gate insulating film are set within ranges expressed by the formula of {.theta.i, t.sub.U .linevert split.0.ltoreq..theta.i.ltoreq.56.6.degree., 0.ltoreq.t.sub.U .ltoreq.0.82t.sub.G }. Thereby, an unetched portion does not remain at an etching step for patterning the gate electrode layer to be formed later. This prevents short-circuit of the gate electrode. Since the element isolating oxide film has the improved flatness, a quantity of overetching in an active region can be reduced at a step of patterning the gate electrode. This prevents shaving of the gate insulating film and the underlying substrate surface.

摘要翻译： 提供了一种半导体器件，其包括具有良好的上部平坦度的元件隔离氧化物膜及其制造方法。 假设tG表示栅电极层6的厚度，从栅极绝缘膜5的上表面到元件隔离氧化膜4的最厚部分的上表面的高度tU和在上表面之间限定的锐角θi 元件隔离氧化膜4和栅极绝缘膜的表面被设置在由公式{θi，tU + 5443 0 = 0.82tG}表示的范围内 。 因此，未蚀刻部分不保留在用于图形化稍后形成的栅极电极层的蚀刻步骤。 这防止了栅电极的短路。 由于元件隔离氧化物膜具有改善的平坦度，所以在图案化栅极电极的步骤中可以减少活性区域中的过蚀刻量。 这防止了栅极绝缘膜和下面的衬底表面的剃刮。

公开(公告)号：US5831323A

公开(公告)日：1998-11-03

申请号：US601662

申请日：1996-02-14

申请人： Kaoru Motonami ,  Shigeru Shiratake ,  Hiroshi Matsuo ,  Yuichi Yokoyama ,  Kenji Morisawa ,  Ritsuko Gotoda ,  Takaaki Murakami ,  Satoshi Hamamoto ,  Kenji Yasumura ,  Yasuyoshi Itoh

发明人： Kaoru Motonami ,  Shigeru Shiratake ,  Hiroshi Matsuo ,  Yuichi Yokoyama ,  Kenji Morisawa ,  Ritsuko Gotoda ,  Takaaki Murakami ,  Satoshi Hamamoto ,  Kenji Yasumura ,  Yasuyoshi Itoh

IPC分类号： H01L21/316 ,  H01L21/76 ,  H01L21/762 ,  H01L21/8234 ,  H01L29/00

CPC分类号： H01L21/823475 ,  H01L21/76205 ,  H01L21/7621 ,  H01L21/76216

摘要： There are provided a semiconductor device, which includes an element isolating oxide film having a good upper flatness, and a method of manufacturing the same. Assuming that t.sub.G represents a thickness of a gate electrode layer 6, a height t.sub.U to an upper surface of a thickest portion of element isolating oxide film 4 from an upper surface of a gate insulating film 5 and an acute angle .theta.i defined between the upper surfaces of element isolating oxide film 4 and gate insulating film are set within ranges expressed by the formula of {.theta.i, t.sub.U .linevert split.0.ltoreq..theta.i.ltoreq.56.6.degree., 0.ltoreq.t.sub.U .ltoreq.0.82t.sub.G }. Thereby, an unetched portion does not remain at an etching step for patterning the gate electrode layer to be formed later. This prevents short-circuit of the gate electrode. Since the element isolating oxide film has the improved flatness, a quantity of overetching in an active region can be reduced at a step of patterning the gate electrode. This prevents shaving of the gate insulating film and the underlying substrate surface.

公开(公告)号：US07239840B2

公开(公告)日：2007-07-03

申请号：US11260314

申请日：2005-10-28

申请人： Kazuhiko Kikuchi ,  Masanori Takai ,  Satoshi Himeno ,  Yuichi Yokoyama ,  Kazuhisa Takeda ,  Yasunari Miyazaki

发明人： Kazuhiko Kikuchi ,  Masanori Takai ,  Satoshi Himeno ,  Yuichi Yokoyama ,  Kazuhisa Takeda ,  Yasunari Miyazaki

IPC分类号： G03G15/20

CPC分类号： G03G15/2057

摘要： A heat fixing member according to the invention has a surface layer formed on the surface of the substrate with a three-layer structure of a primer layer, an middle layer, and a topcoat layer. The binder-resin content decreases in order from the primer layer to the topcoat layer. The fluorocarbon-resin content increases in order from the primer layer to the topcoat layer. The topcoat layer is made of a fluorocarbon resin having high ability of release and a fluorocarbon resin having high abrasion resistance. Thus, the surface layer can be prevented from peeling without losing ability of release and can be decreased in abrasion.

摘要翻译： 根据本发明的热固定构件具有在基底表面上形成有底层，中间层和顶涂层的三层结构的表面层。 粘合剂 - 树脂含量从底涂层到顶涂层依次降低。 氟碳树脂含量从底涂层到顶涂层依次增加。 顶涂层由具有高释放能力的氟碳树脂和具有高耐磨性的氟碳树脂制成。 因此，可以防止表面层剥离而不丧失剥离能力，并且可以减少磨损。

公开(公告)号：US5905124A

公开(公告)日：1999-05-18

申请号：US837888

申请日：1997-04-22

申请人： Noriyuki Shoji ,  Masashi Nomura ,  Yuichi Yokoyama

发明人： Noriyuki Shoji ,  Masashi Nomura ,  Yuichi Yokoyama

IPC分类号： G02C7/04 ,  A61L27/00 ,  C08F2/00 ,  C08F2/44 ,  C08F4/06 ,  C08F6/00 ,  C08F6/06 ,  C08F20/26 ,  C08F20/28 ,  C08F220/28 ,  C08K5/02 ,  C08L33/10 ,  G02B1/04

CPC分类号： C08F20/28 ,  G02B1/043

摘要： A method for producing 2-hydroxyethyl methacrylate polymers comprising polymerizing 2-hydroxyethyl methacrylate or a monomer mixture thereof containing a halogen compound thorough radical polymerization; method for producing hydrogels comprising subjecting the polymers to a water-imparting treatment; method for producing water-containing soft contact lenses comprising molding the polymers into a shape of contact lens and subjecting them to a water-imparting treatment and method for producing polymers comprising treating at least molding surfaces of molds, which form a cavity of contact lens shape, with a halogen compound and polymerizing 2-hydroxyethyl methacrylate or a monomer mixture thereof in the cavity through radical polymerization are disclosed. According to the present invention, water-containing soft contact lenses with high heat resistance and intermediates therefor are obtained from 2-hydroxyethyl methacrylate of high purity.

摘要翻译： 一种生产甲基丙烯酸2-羟乙酯聚合物的方法，其包括聚合甲基丙烯酸2-羟乙酯或其中含卤素化合物的单体混合物进行彻底自由基聚合; 制造水凝胶的方法，包括使聚合物进行水赋予处理; 制造含水软性隐形眼镜的方法包括将聚合物模塑成隐形眼镜的形状并对其进行赋水处理和生产聚合物的方法，包括至少处理形成隐形眼镜形状的腔的模具的模制表面 ，通过自由基聚合在空腔中通过卤素化合物和甲基丙烯酸2-羟乙酯或其单体混合物聚合。 根据本发明，从高纯度的甲基丙烯酸2-羟乙酯获得具有高耐热性的含水软性隐形眼镜及其中间体。

公开(公告)号：US5900554A

公开(公告)日：1999-05-04

申请号：US3711

申请日：1998-01-07

申请人： Horonobu Baba ,  Tiaki Mizuno ,  Masahito Imai ,  Yuichi Yokoyama ,  Masaki Takakuwa ,  Yasuki Shimoyama

发明人： Horonobu Baba ,  Tiaki Mizuno ,  Masahito Imai ,  Yuichi Yokoyama ,  Masaki Takakuwa ,  Yasuki Shimoyama

IPC分类号： G01L9/00 ,  G01L9/04

CPC分类号： G01L19/147 ,  G01L19/0038 ,  G01L19/0084 ,  G01L19/0636 ,  G01L19/143

摘要： When a compressed air is led into a reference pressure chamber along with a boundary between a resin housing and a terminal, such compressed air may cause a wire breaking. A barrier wall for blocking the compressed air from penetrating toward the wire is disposed. The reference pressure chamber is divided into a main chamber and a subchamber by the barrier wall. Since the barrier wall blocks the compressed air, the compressed air can not reach a silicon gel in the main chamber. Therefore, the wire breaking caused by the compressed air when connecting a connector therewith can be precluded.

摘要翻译： 当压缩空气与树脂壳体和端子之间的边界一起被引入参考压力室时，这种压缩空气可能导致断线。 设置用于阻挡压缩空气渗透到线的阻挡壁。 基准压力室由隔离壁分为主室和副室。 由于阻隔壁阻挡压缩空气，所以压缩空气不能到达主室中的硅凝胶。 因此，可以防止在连接连接器时由压缩空气引起的断线。