公开(公告)号：US06461977B1

公开(公告)日：2002-10-08

申请号：US09417086

申请日：1999-10-13

申请人： Hiroshi Matsuo ,  Takuji Oda ,  Yuichi Yokoyama ,  Kiyoshi Maeda ,  Shinya Inoue ,  Yuji Yamamoto

发明人： Hiroshi Matsuo ,  Takuji Oda ,  Yuichi Yokoyama ,  Kiyoshi Maeda ,  Shinya Inoue ,  Yuji Yamamoto

IPC分类号： H01L21302

CPC分类号： H01L21/67069 ,  H01L21/31116 ,  H01L21/76897

摘要： An improved etching method allowing the formation of a silicon nitride film with an adequate film thickness at the sidewall portion of a pattern is disclosed. A silicon nitride film formed to cover a stepped pattern is dry-etched, employing plasma of mixed gases containing CH2F2 and O2. As a result, a sidewall spacer of the silicon nitride film is formed at the sidewall of the pattern in a self-aligned manner.

摘要翻译： 公开了一种改进的蚀刻方法，其允许在图案的侧壁部分处形成具有适当膜厚度的氮化硅膜。 用包含CH 2 F 2和O 2的混合气体的等离子体干蚀刻形成为覆盖阶梯图案的氮化硅膜。 结果，氮化硅膜的侧壁间隔物以自对准的方式形成在图案的侧壁处。

公开(公告)号：US06444515B2

公开(公告)日：2002-09-03

申请号：US09761176

申请日：2001-01-18

申请人： Hiroshi Matsuo ,  Yuichi Yokoyama ,  Takuji Oda ,  Kiyoshi Maeda ,  Shinya Inoue ,  Yuji Yamamoto

发明人： Hiroshi Matsuo ,  Yuichi Yokoyama ,  Takuji Oda ,  Kiyoshi Maeda ,  Shinya Inoue ,  Yuji Yamamoto

IPC分类号： H01L218238

CPC分类号： H01L27/10873 ,  H01L21/76805 ,  H01L21/76897 ,  H01L23/485 ,  H01L27/10888 ,  H01L27/10894 ,  H01L2924/0002 ,  H01L2924/00

摘要： A hard mask insulating layer is formed on a gate electrode which is formed on a main surface of a silicon substrate with a gate insulating layer interposed. An SiN sidewall spacer is directly formed on a thin SiO2 layer which is formed to cover a side surface of the gate electrode. A contact hole is formed to penetrate an interlayer insulating layer formed on an SiN stopper layer and reach the main surface of the silicon substrate.

摘要翻译： 在栅极电极上形成硬掩模绝缘层，栅电极形成在硅衬底的主表面上，栅极绝缘层被插入。 SiN侧壁间隔物直接形成在形成为覆盖栅电极的侧表面的薄SiO 2层上。 形成接触孔以穿透形成在SiN阻挡层上的层间绝缘层并到达硅衬底的主表面。

公开(公告)号：US5994227A

公开(公告)日：1999-11-30

申请号：US119045

申请日：1998-07-20

申请人： Hiroshi Matsuo ,  Takuji Oda ,  Yuichi Yokoyama ,  Kiyoshi Maeda ,  Shinya Inoue ,  Yuji Yamamoto

发明人： Hiroshi Matsuo ,  Takuji Oda ,  Yuichi Yokoyama ,  Kiyoshi Maeda ,  Shinya Inoue ,  Yuji Yamamoto

IPC分类号： H01L21/28 ,  H01L21/00 ,  H01L21/302 ,  H01L21/3065 ,  H01L21/311 ,  H01L21/60 ,  H01L21/8242 ,  H01L21/8244 ,  H01L27/108 ,  H01L27/11

CPC分类号： H01L21/67069 ,  H01L21/31116 ,  H01L21/76897

摘要： An improved etching method allowing the formation of a silicon nitride film with an adequate film thickness at the sidewall portion of a pattern is disclosed. A silicon nitride film formed to cover a stepped pattern is dry-etched, employing plasma of mixed gases containing CH.sub.2 F.sub.2 and O.sub.2. As a result, a sidewall spacer of the silicon nitride film is formed at the sidewall of the pattern in a self-aligned manner.

公开(公告)号：US06249015B1

公开(公告)日：2001-06-19

申请号：US09115514

申请日：1998-07-15

申请人： Hiroshi Matsuo ,  Yuichi Yokoyama ,  Takuji Oda ,  Kiyoshi Maeda ,  Shinya Inoue ,  Yuji Yamamoto

发明人： Hiroshi Matsuo ,  Yuichi Yokoyama ,  Takuji Oda ,  Kiyoshi Maeda ,  Shinya Inoue ,  Yuji Yamamoto

IPC分类号： H01L27108

CPC分类号： H01L27/10873 ,  H01L21/76805 ,  H01L21/76897 ,  H01L23/485 ,  H01L27/10888 ,  H01L27/10894 ,  H01L2924/0002 ,  H01L2924/00

摘要： A hard mask insulating layer is formed on a gate electrode which is formed on a main surface of a silicon substrate with a gate insulating layer interposed. An SiN sidewall spacer is directly formed on a thin SiO2 layer which is formed to cover a side surface of the gate electrode. A contact hole is formed to penetrate an interlayer insulating layer formed on an SiN stopper layer and reach the main surface of the silicon substrate.

公开(公告)号：US5747843A

公开(公告)日：1998-05-05

申请号：US667684

申请日：1996-06-21

申请人： Hiroshi Matsuo ,  Shinya Watanabe ,  Yuichi Yokoyama ,  Shinya Inoue

发明人： Hiroshi Matsuo ,  Shinya Watanabe ,  Yuichi Yokoyama ,  Shinya Inoue

IPC分类号： G11C11/4099 ,  H01L21/8242 ,  H01L27/105 ,  H01L27/108 ,  G11C5/02 ,  G11C13/00

CPC分类号： G11C11/4099 ,  H01L27/105 ,  H01L27/108

摘要： An improved semiconductor memory device in which an electric circuit operates normally is provided. A block of memory cells of a dynamic random access memory is provided on a semiconductor substrate. A dummy storage node is provided near a corner portion of the memory cell block. A dummy cell plate is provided such that it covers the dummy storage node and is electrically insulated from a main cell plate of the DRAM.

摘要翻译： 提供其中电路正常工作的改进的半导体存储器件。 动态随机存取存储器的存储单元块被提供在半导体衬底上。 在存储单元块的角部附近提供虚拟存储节点。 提供虚拟单元板，使得其覆盖虚拟存储节点并且与DRAM的主单元电池电绝缘。

公开(公告)号：US6033971A

公开(公告)日：2000-03-07

申请号：US160379

申请日：1998-09-25

申请人： Kaoru Motonami ,  Shigeru Shiratake ,  Hiroshi Matsuo ,  Yuichi Yokoyama ,  Kenji Morisawa ,  Ritsuko Gotoda ,  Takaaki Murakami ,  Satoshi Hamamoto ,  Kenji Yasumura ,  Yasuyoshi Itoh

发明人： Kaoru Motonami ,  Shigeru Shiratake ,  Hiroshi Matsuo ,  Yuichi Yokoyama ,  Kenji Morisawa ,  Ritsuko Gotoda ,  Takaaki Murakami ,  Satoshi Hamamoto ,  Kenji Yasumura ,  Yasuyoshi Itoh

IPC分类号： H01L21/316 ,  H01L21/76 ,  H01L21/762 ,  H01L21/8234

CPC分类号： H01L21/823475 ,  H01L21/76205 ,  H01L21/7621 ,  H01L21/76216

摘要： There are provided a semiconductor device, which includes an element isolating oxide film having a good upper flatness, and a method of manufacturing the same. Assuming that t.sub.G represents a thickness of a gate electrode layer 6, a height t.sub.U to an upper surface of a thickest portion of element isolating oxide film 4 from an upper surface of a gate insulating film 5 and an acute angle .theta.i defined between the upper surfaces of element isolating oxide film 4 and gate insulating film are set within ranges expressed by the formula of {.theta.i, t.sub.U .linevert split.0.ltoreq..theta.i.ltoreq.56.6.degree., 0.ltoreq.t.sub.U .ltoreq.0.82t.sub.G }. Thereby, an unetched portion does not remain at an etching step for patterning the gate electrode layer to be formed later. This prevents short-circuit of the gate electrode. Since the element isolating oxide film has the improved flatness, a quantity of overetching in an active region can be reduced at a step of patterning the gate electrode. This prevents shaving of the gate insulating film and the underlying substrate surface.

摘要翻译： 提供了一种半导体器件，其包括具有良好的上部平坦度的元件隔离氧化物膜及其制造方法。 假设tG表示栅电极层6的厚度，从栅极绝缘膜5的上表面到元件隔离氧化膜4的最厚部分的上表面的高度tU和在上表面之间限定的锐角θi 元件隔离氧化膜4和栅极绝缘膜的表面被设置在由公式{θi，tU + 5443 0 = 0.82tG}表示的范围内 。 因此，未蚀刻部分不保留在用于图形化稍后形成的栅极电极层的蚀刻步骤。 这防止了栅电极的短路。 由于元件隔离氧化物膜具有改善的平坦度，所以在图案化栅极电极的步骤中可以减少活性区域中的过蚀刻量。 这防止了栅极绝缘膜和下面的衬底表面的剃刮。

公开(公告)号：US5831323A

公开(公告)日：1998-11-03

申请号：US601662

申请日：1996-02-14

申请人： Kaoru Motonami ,  Shigeru Shiratake ,  Hiroshi Matsuo ,  Yuichi Yokoyama ,  Kenji Morisawa ,  Ritsuko Gotoda ,  Takaaki Murakami ,  Satoshi Hamamoto ,  Kenji Yasumura ,  Yasuyoshi Itoh

发明人： Kaoru Motonami ,  Shigeru Shiratake ,  Hiroshi Matsuo ,  Yuichi Yokoyama ,  Kenji Morisawa ,  Ritsuko Gotoda ,  Takaaki Murakami ,  Satoshi Hamamoto ,  Kenji Yasumura ,  Yasuyoshi Itoh

IPC分类号： H01L21/316 ,  H01L21/76 ,  H01L21/762 ,  H01L21/8234 ,  H01L29/00

CPC分类号： H01L21/823475 ,  H01L21/76205 ,  H01L21/7621 ,  H01L21/76216

摘要： There are provided a semiconductor device, which includes an element isolating oxide film having a good upper flatness, and a method of manufacturing the same. Assuming that t.sub.G represents a thickness of a gate electrode layer 6, a height t.sub.U to an upper surface of a thickest portion of element isolating oxide film 4 from an upper surface of a gate insulating film 5 and an acute angle .theta.i defined between the upper surfaces of element isolating oxide film 4 and gate insulating film are set within ranges expressed by the formula of {.theta.i, t.sub.U .linevert split.0.ltoreq..theta.i.ltoreq.56.6.degree., 0.ltoreq.t.sub.U .ltoreq.0.82t.sub.G }. Thereby, an unetched portion does not remain at an etching step for patterning the gate electrode layer to be formed later. This prevents short-circuit of the gate electrode. Since the element isolating oxide film has the improved flatness, a quantity of overetching in an active region can be reduced at a step of patterning the gate electrode. This prevents shaving of the gate insulating film and the underlying substrate surface.

公开(公告)号：US08138449B2

公开(公告)日：2012-03-20

申请号：US12466635

申请日：2009-05-15

申请人： Naoyuki Matsuo ,  Hiroshi Matsuo

发明人： Naoyuki Matsuo ,  Hiroshi Matsuo

IPC分类号： B23K26/20 ,  B29C65/16

CPC分类号： B21C47/247 ,  B23K26/211 ,  B23K26/244 ,  B23K33/004 ,  B23K2101/16 ,  B23K2101/18 ,  B29C65/1616 ,  B29C65/1629 ,  B29C65/1635 ,  B29C65/1658 ,  B29C65/1664 ,  B29C65/1677 ,  B29C65/168 ,  B29C65/4815 ,  B29C65/5042 ,  B29C65/5057 ,  B29C65/72 ,  B29C66/1122 ,  B29C66/1142 ,  B29C66/21 ,  B29C66/232 ,  B29C66/3452 ,  B29C66/43 ,  B29C66/71 ,  B29C66/72321 ,  B29C66/729 ,  B29C66/7352 ,  B29C66/73921 ,  B29C66/73941 ,  B29C66/83411 ,  B29C66/83415 ,  B29C2035/0822 ,  B29K2007/00 ,  B29K2023/06 ,  B29K2023/12 ,  B29K2023/16 ,  B29K2063/00 ,  B29K2067/00 ,  B29K2101/10 ,  B29K2101/12 ,  B29K2105/0854 ,  B29K2311/10 ,  B29K2313/00 ,  B29L2009/00 ,  B65H19/1836 ,  B65H19/20 ,  B65H2301/4621 ,  B65H2301/46222 ,  B65H2301/4631 ,  B65H2301/516 ,  B65H2701/1313 ,  B29K2023/04 ,  B29K2023/10 ,  B29K2067/003 ,  B29K2059/00

摘要： A method of joining sheet members together, which enables two sheets to be joined while conveying these sheets and reducing a cause of inferior products as much as possible. The method of joining sheet members includes: bonding an end of a new sheet member to a surface of a preceding sheet member through an adhesive material to form a joined part; and cutting the preceding sheet member at a position rearward of the joined part to join the preceding sheet member with a new sheet member, wherein the preceding sheet member is secured to the new sheet at a position rearward of the joined part. In addition, in the method of joining sheet members, the securing is carried out by welding using laser beam.

摘要翻译： 一种将片材部件接合在一起的方法，其能够在输送这些片材的同时使两张片材接合，并尽可能地减少劣质产品的原因。 接合片材的方法包括：通过粘合剂材料将新片材的端部粘合到前一片材的表面以形成接合部分; 并且在接合部分的后方的位置处切割前述片状部件，以使前述片材部件与新的片状部件接合，其中，前述片材部件在接合部件的后方的位置固定在新的片材上。 此外，在接合片材的方法中，通过使用激光束的焊接进行固定。

公开(公告)号：US20080130205A1

公开(公告)日：2008-06-05

申请号：US11984434

申请日：2007-11-16

申请人： Hiroshi Matsuo

发明人： Hiroshi Matsuo

IPC分类号： H05K7/00

CPC分类号： H03H9/1071

摘要： A surface acoustic wave device includes a base portion that surrounds a surface acoustic wave element and is made of a resin, and a cap portion that is adhered onto the base portion so that a cavity sealing the surface acoustic wave element is formed, and is made of a resin. At least one of an adhering face of the base portion and an adhering face of the cap portion adhering the base portion and the cap portion is subjected to a grain finish or a dull finish. A convex portion is provided inside of the adhering face that is of one of the base portion and the cap portion adhered to the other.

摘要翻译： 声表面波装置包括：包围声表面波元件的基部，由树脂构成的盖部;粘贴于基部的盖部，形成密封声表面波元的空腔; 的树脂。 基部的粘合面和粘贴基部和盖部的盖部的粘接面中的至少一个受到谷物磨光或钝化。 在基体部分和盖部分中的一个粘附到另一个的粘附面的内侧设置凸部。

公开(公告)号：US06552314B2

公开(公告)日：2003-04-22

申请号：US09833877

申请日：2001-04-12

申请人： Kei Fukushima ,  Hiroshi Matsuo

发明人： Kei Fukushima ,  Hiroshi Matsuo

IPC分类号： H05B668

CPC分类号： H05B6/6447 ,  Y10T292/11

摘要： A normal position detecting mechanism for detecting a position of a functional component in a heating apparatus includes a drive member mounted on the functional component, a drive unit assembly mounted on the heating apparatus, and a switch for generating a detection signal. The driven unit assembly includes a switch actuating member, a bracket for supporting the switch actuating member, and a biasing member arranged between the mounting bracket and the switch. The biasing member applies a bias force for driving the switch actuating member against the direction for generating the detection signal. The drive member is positioned facing the switch actuating member when the functional component is in its normal position so that the drive member provides a force to move the switch against the biasing force to generate a detection signal.

摘要翻译： 用于检测加热装置中的功能部件的位置的正常位置检测机构包括安装在功能部件上的驱动部件，安装在加热装置上的驱动部件组件和产生检测信号的开关。 从动单元组件包括开关致动构件，用于支撑开关致动构件的支架和布置在安装支架和开关之间的偏置构件。 偏压构件抵抗用于产生检测信号的方向施加用于驱动开关致动构件的偏压力。 当功能部件处于其正常位置时，驱动部件定位成面向开关致动部件，使得驱动部件提供力以使该开关抵抗偏置力移动以产生检测信号。