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    Method for managing construction machine, and arithmetic processing apparatus
    3.
    发明授权
    Method for managing construction machine, and arithmetic processing apparatus 有权
    施工机械管理方法及运算处理装置

    公开(公告)号：US06832175B2

    公开(公告)日：2004-12-14

    申请号：US10240117

    申请日：2002-09-27

    申请人： Hiroyuki Adachi ,  Toichi Hirata ,  Genroku Sugiyama ,  Hiroshi Watanabe ,  Shuichi Miura ,  Koji Mitsuya ,  Yoshiaki Saito ,  Atsushi Sato

    发明人： Hiroyuki Adachi ,  Toichi Hirata ,  Genroku Sugiyama ,  Hiroshi Watanabe ,  Shuichi Miura ,  Koji Mitsuya ,  Yoshiaki Saito ,  Atsushi Sato

    IPC分类号： G04F100

    CPC分类号： E02F9/20 ,  G07C5/008 ,  G07C5/085

    摘要： A hydraulic excavator 1 working in fields includes a controller 2 for measuring a working time for each of an engine 32, a front 15, a swing body 13, and a travel body 12, storing measured data in a memory of the controller 2, and then transferring it to a base station computer 3 via satellite communication, an FD, etc. The transferred data is stored as a database 100 in the base station computer 3. The base station computer 3 reads the data stored in the database 100 for each hydraulic excavator, calculates a working time of a part belonging to each section on the basis of the working time of that section, and compares the calculated working time with a preset target replacement time interval of the relevant part, thereby calculating a remaining time up to next replacement of the relevant part and managing the scheduled replacement timing thereof. Thus, the appropriate scheduled replacement timing of parts can be determined even in a construction machine having a plurality of sections that differ in working time from each other.

    摘要翻译： 在田间工作的液压挖掘机1包括控制器2，用于测量发动机32，前15，摆动体13和行驶体12的工作时间，将测量数据存储在控制器2的存储器中，以及 然后通过卫星通信，FD等将其传送到基站计算机3.将传送的数据作为数据库100存储在基站计算机3中。基站计算机3读取存储在数据库100中的每个液压的数据 挖掘机根据该部分的工作时间计算属于每个部分的部分的工作时间，并将计算出的工作时间与相关部分的预设目标更换时间间隔进行比较，从而计算直至下一个的剩余时间 更换相关部件并管理其定时更换时间。 因此，即使在具有彼此不同的工作时间的多个部分的建筑机械中，也可以确定部件的适当的计划更换定时。

    AUTOMATIC ANALYZER
    5.
    发明申请
    AUTOMATIC ANALYZER 审中-公开
    自动分析仪

    公开(公告)号：US20140170023A1

    公开(公告)日：2014-06-19

    申请号：US14236659

    申请日：2012-06-29

    申请人： Yoshiaki Saito ,  Kazuhiro Nakamura ,  Naoto Suzuki ,  Toshihide Orihashi

    发明人： Yoshiaki Saito ,  Kazuhiro Nakamura ,  Naoto Suzuki ,  Toshihide Orihashi

    IPC分类号： G01N35/04

    CPC分类号： G01N35/04 ,  G01N35/0095 ,  G01N35/026 ,  G01N2035/0415 ,  G01N2035/0462

    摘要： In determining whether a rack inputted to the automatic analyzer by the user is to be transferred to an analysis section or not, samples existing in a route from a buffer to a sample dispensing position in the analysis section are identified, and the number of items in which suction by a nozzle has not been completed in analysis items requested for the samples is managed. When the number of items is reduced to be smaller than a given number, the conveyance of a next rack from the buffer to the analysis section is controlled, thereby limiting the number of analysis items requested for samples in a waiting state for analysis in the analysis section constantly to be smaller than a fixed number. As a result, a period of time until a measurement result of emergency samples is outputted can be reduced even when emergency samples are newly inputted.

    摘要翻译： 在确定用户输入到自动分析器的机架是否要转移到分析部分时，识别存在于分析部分中从缓冲器到样品分配位置的路线中的样本，并且在 在对样品所要求的分析项目进行管理的情况下，由喷嘴抽吸尚未完成。 当项目数量减少到小于给定数量时，控制从缓冲器到分析部分的下一个机架的传送，从而限制在分析中用于分析的等待状态下的样品请求的分析项目的数量 部分不断小于固定数。 结果，直到紧急样本的测量结果输出的时间段即使在新输入紧急样本时也可以减少。

    Working vehicle, control device for working vehicle, and hydraulic oil amount control method for working vehicle
    6.
    发明授权
    Working vehicle, control device for working vehicle, and hydraulic oil amount control method for working vehicle 有权
    工作车辆，作业车辆控制装置以及工作车辆的液压油量控制方法

    公开(公告)号：US08725358B2

    公开(公告)日：2014-05-13

    申请号：US12736159

    申请日：2009-03-11

    申请人： Takahide Takiguchi ,  Satoshi Matsumoto ,  Yoshiaki Saito

    发明人： Takahide Takiguchi ,  Satoshi Matsumoto ,  Yoshiaki Saito

    IPC分类号： E02F9/22 ,  G06F19/00 ,  E02F3/43 ,  F15B11/00

    CPC分类号： E02F9/2246 ,  E02F9/2235 ,  E02F9/2296

    摘要： An object of the present invention is to prevent an unnecessary large amount of hydraulic oil from being supplied to a cylinder when a working vehicle capable of performing both a loading operation and a digging operation is performing the digging operation. When one or a plurality of first digging operation conditions are satisfied and when a second operation condition that it is not detected that the loading operation is being performed is also satisfied, a control unit executes fluid amount reduction control of reducing the amount of hydraulic oil supplied from a first pump to a cylinder that actuates a work equipment.

    摘要翻译： 本发明的目的在于，当能够执行装载操作和挖掘操作的作业车辆正在进行挖掘操作时，防止不必要的大量液压油被供给到气缸。 当满足一个或多个第一挖掘操作条件时，并且当满足未检测到正在进行装载操作的第二操作条件时，控制单元执行减少供应的液压油量的流体量减少控制 从第一泵到致动工作设备的气缸。

    Analog-to-digital converter for dividing reference voltage using plural variable resistors
    7.
    发明授权
    Analog-to-digital converter for dividing reference voltage using plural variable resistors 失效
    用于使用多个可变电阻器分压参考电压的模数转换器

    公开(公告)号：US08681034B2

    公开(公告)日：2014-03-25

    申请号：US13536085

    申请日：2012-06-28

    申请人： Takao Marukame ,  Tetsufumi Tanamoto ,  Atsuhiro Kinoshita ,  Tomoaki Inokuchi ,  Masamichi Suzuki ,  Yoshiaki Saito

    发明人： Takao Marukame ,  Tetsufumi Tanamoto ,  Atsuhiro Kinoshita ,  Tomoaki Inokuchi ,  Masamichi Suzuki ,  Yoshiaki Saito

    IPC分类号： H03M1/34

    CPC分类号： H03M1/1061 ,  H01L27/22 ,  H01L43/08 ,  H03M1/365

    摘要： According to an embodiment, an analog-to-digital converter includes a voltage generating unit, and a plurality of comparators. The voltage generating unit is configured to divide a reference voltage by a plurality of variable resistors to generate a plurality of comparative voltages. Each of the plurality of comparator is configured to compare any one of the plurality of comparative voltages with an analog input voltage and output a digital signal based on a result of a comparison between the comparative voltage and the analog input voltage. Each of the plurality of variable resistors includes a plurality of variable resistive elements that are connected in series, and each of the plurality of variable resistive elements has a resistance value that is variably set according to an external signal.

    摘要翻译： 根据实施例，模数转换器包括电压产生单元和多个比较器。 电压产生单元被配置为通过多个可变电阻器分压参考电压以产生多个比较电压。 多个比较器中的每一个被配置为将多个比较电压中的任何一个与模拟输入电压进行比较，并且基于比较电压和模拟输入电压之间的比较结果输出数字信号。 多个可变电阻器中的每一个包括串联连接的多个可变电阻元件，并且多个可变电阻元件中的每一个具有根据外部信号可变地设置的电阻值。

    Analog-to-digital converter including differential pair circuit
    8.
    发明授权
    Analog-to-digital converter including differential pair circuit 失效
    模数转换器包括差分对电路

    公开(公告)号：US08681033B2

    公开(公告)日：2014-03-25

    申请号：US13535118

    申请日：2012-06-27

    申请人： Takao Marukame ,  Tetsufumi Tanamoto ,  Atsuhiro Kinoshita ,  Tomoaki Inokuchi ,  Masamichi Suzuki ,  Yoshiaki Saito

    发明人： Takao Marukame ,  Tetsufumi Tanamoto ,  Atsuhiro Kinoshita ,  Tomoaki Inokuchi ,  Masamichi Suzuki ,  Yoshiaki Saito

    IPC分类号： H03M1/34

    CPC分类号： H03M1/1061 ,  H03F3/45183 ,  H03F2203/45391 ,  H03F2203/45392 ,  H03F2203/45674 ,  H03K5/2481 ,  H03M1/365

    摘要： According to an embodiment, an analog-to-digital converter includes a voltage generating unit to generate comparative voltages; and comparators. Each comparator compares any one of the comparative voltages with an analog input voltage and output a digital signal. Each comparator includes a differential pair circuit to detect a potential difference between two inputs. The differential pair circuit includes first and second circuit portions. The first circuit portion includes a first transistor having a gate to which one input is supplied; and a resistor connected in series with the first transistor. The second circuit portion includes a second transistor having a gate to which the other input is supplied and forms a differential pair with the first transistor; and a variable resistor connected in series with the second transistor. The variable resistor includes variable resistive elements each having a resistance value variably set according to a control signal.

    摘要翻译： 根据实施例，模数转换器包括产生比较电压的电压产生单元; 和比较者。 每个比较器将比较电压中的任何一个与模拟输入电压进行比较，并输出数字信号。 每个比较器包括用于检测两个输入之间的电位差的差分对电路。 差分对电路包括第一和第二电路部分。 第一电路部分包括具有一个输入端的栅极的第一晶体管; 以及与第一晶体管串联连接的电阻器。 第二电路部分包括第二晶体管，其具有提供另一输入的栅极，并与第一晶体管形成差分对; 以及与第二晶体管串联连接的可变电阻器。 可变电阻器包括可变电阻元件，每个电阻元件具有根据控制信号可变地设置的电阻值。

    Spin MOSFET and reconfigurable logic circuit
    9.
    发明授权
    Spin MOSFET and reconfigurable logic circuit 有权
    旋转MOSFET和可重构逻辑电路

    公开(公告)号：US08637946B2

    公开(公告)日：2014-01-28

    申请号：US13228852

    申请日：2011-09-09

    申请人： Yoshiaki Saito ,  Hideyuki Sugiyama ,  Tomoaki Inokuchi ,  Takao Marukame ,  Mizue Ishikawa

    发明人： Yoshiaki Saito ,  Hideyuki Sugiyama ,  Tomoaki Inokuchi ,  Takao Marukame ,  Mizue Ishikawa

    IPC分类号： H01L29/82

    CPC分类号： H01L43/02 ,  B01D53/1493 ,  B01D53/62 ,  G11C11/16 ,  G11C11/161 ,  G11C11/1673 ,  G11C11/1675 ,  G11C11/1695 ,  H01L28/00 ,  H01L29/0843 ,  H01L29/0895 ,  H01L29/66984 ,  H01L43/10

    摘要： A spin MOSFET includes: a first ferromagnetic layer provided on a semiconductor substrate, and having a fixed magnetization direction perpendicular to a film plane; a semiconductor layer provided on the first ferromagnetic layer, including a lower face opposed to the upper face of the first ferromagnetic layer, an upper face opposed to the lower face, and side faces different from the lower and upper faces; a second ferromagnetic layer provided on the upper face of the semiconductor layer, and having a variable magnetization direction perpendicular to a film plane; a first tunnel barrier provided on the second ferromagnetic layer; a third ferromagnetic layer provided on the first tunnel barrier; a gate insulating film provided on the side faces of the semiconductor layer; and a gate electrode provided on the side faces of the semiconductor layer with the gate insulating film being interposed therebetween.

    摘要翻译： 自旋MOSFET包括：设置在半导体衬底上并具有与膜平面垂直的固定磁化方向的第一铁磁层; 设置在所述第一铁磁层上的半导体层，包括与所述第一铁磁层的上表面相对的下表面，与所述下表面相对的上表面，以及与所述下表面和所述上表面不同的侧面; 第二铁磁层，设置在所述半导体层的上表面上，并且具有与膜平面垂直的可变磁化方向; 设置在第二铁磁层上的第一隧道势垒; 设置在第一隧道屏障上的第三铁磁层; 设置在所述半导体层的侧面上的栅极绝缘膜; 以及设置在半导体层的侧面上的栅电极，其间插入有栅极绝缘膜。

    Memory circuit using spin MOSFETs, path transistor circuit with memory function, switching box circuit, switching block circuit, and field programmable gate array
    10.
    发明授权
    Memory circuit using spin MOSFETs, path transistor circuit with memory function, switching box circuit, switching block circuit, and field programmable gate array 有权
    使用自旋MOSFET的存储电路，具有存储功能的路径晶体管电路，开关盒电路，开关块电路和现场可编程门阵列

    公开(公告)号：US08611143B2

    公开(公告)日：2013-12-17

    申请号：US13403308

    申请日：2012-02-23

    申请人： Hideyuki Sugiyama ,  Masato Oda ,  Shinobu Fujita ,  Tetsufumi Tanamoto ,  Mizue Ishikawa ,  Takao Marukame ,  Tomoaki Inokuchi ,  Yoshiaki Saito

    发明人： Hideyuki Sugiyama ,  Masato Oda ,  Shinobu Fujita ,  Tetsufumi Tanamoto ,  Mizue Ishikawa ,  Takao Marukame ,  Tomoaki Inokuchi ,  Yoshiaki Saito

    IPC分类号： G11C11/00

    CPC分类号： G11C5/148 ,  G11C11/161 ,  G11C11/1673 ,  G11C11/1675

    摘要： A memory circuit according to an embodiment includes: a first transistor including a first source/drain electrode, a second source/drain electrode, and a first gate electrode; a second transistor including a third source/drain electrode connected to the second source/drain electrode, a fourth source/drain electrode, and a second gate electrode; a third transistor and a fourth transistor forming an inverter circuit, the third transistor including a fifth source/drain electrode, a sixth source/drain electrode, and a third gate electrode connected to the second source/drain electrode, the fourth transistor including a seventh source/drain electrode connected to the sixth source/drain electrode, an eighth source/drain electrode, and a fourth gate electrode connected to the second source/drain electrode; and an output terminal connected to the sixth source/drain electrode. At least one of the third transistor and the fourth transistor is a spin MOSFET, and an output of the inverter circuit is sent from the output terminal.

    摘要翻译： 根据实施例的存储器电路包括：第一晶体管，包括第一源极/漏极，第二源极/漏极和第一栅电极; 第二晶体管，包括连接到第二源极/漏极的第三源极/漏极，第四源极/漏极和第二栅极; 第三晶体管和形成逆变器电路的第四晶体管，所述第三晶体管包括第五源极/漏极，第六源极/漏极和连接到所述第二源极/漏极的第三栅电极，所述第四晶体管包括第七 连接到第六源极/漏极的源极/漏极电极，连接到第二源极/漏极的第八源极/漏极电极和第四栅极电极; 以及连接到第六源极/漏极的输出端子。 第三晶体管和第四晶体管中的至少一个是自旋MOSFET，并且从输出端子发送反相器电路的输出。