公开(公告)号：US07514802B2

公开(公告)日：2009-04-07

申请号：US11531381

申请日：2006-09-13

Applicant: Michinari Tetani ,  Takayuki Tanaka ,  Hiroyuki Imamura ,  Nozomi Shimoishizaka ,  Kouichi Nagao

Inventor： Michinari Tetani ,  Takayuki Tanaka ,  Hiroyuki Imamura ,  Nozomi Shimoishizaka ,  Kouichi Nagao

IPC: H01L23/544

CPC classification number: H01L23/544 ,  H01L23/4985 ,  H01L24/81 ,  H01L2223/5442 ,  H01L2223/54473 ,  H01L2224/81121 ,  H01L2224/81192 ,  H01L2224/81801 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H05K1/0269 ,  H05K1/0393 ,  H05K3/0097 ,  H05K3/303 ,  H05K2201/0367 ,  H05K2201/09781 ,  H05K2201/09918 ,  H05K2201/10674 ,  H05K2203/1545 ,  H05K2203/166

Abstract: A flexible insulating base, a plurality of conductor wirings aligned on the flexible insulating base, and bump electrodes provided respectively in end portions of the plurality of conductor wirings in a region where a semiconductor chip is to be placed are provided. The semiconductor chip is mounted on the conductor wirings by bonding electrode pads formed on the semiconductor chip to the bump electrodes. An auxiliary conductor wiring formed similarly to the conductor wirings is provided on the insulating base, and an auxiliary bump electrode formed similarly to the bump electrodes is provided on the auxiliary conductor wiring, so that the electrode pads formed on the semiconductor chip can be registered with respect to the bump electrodes on the conductor wirings by positioning the semiconductor chip with reference to the auxiliary bump electrode. It is possible to configure a wiring board having register marks capable of positioning electrode pads of a semiconductor chip with respect to bump electrodes with high accuracy.

Abstract translation: 提供柔性绝缘基座，在柔性绝缘基座上对准的多个导体布线和分别设置在要放置半导体芯片的区域中的多个导体布线的端部中的凸起电极。 通过将形成在半导体芯片上的电极焊盘接合到凸块电极，将半导体芯片安装在导体布线上。 在导体布线上形成类似于导体布线的辅助导体布线设置在绝缘基底上，并且在辅助导体布线上设置类似于隆起电极形成的辅助凸起电极，使得形成在半导体芯片上的电极焊盘可以被注册 通过相对于辅助凸起电极定位半导体芯片，相对于导体布线上的凸块电极。 可以配置具有能够高精度地相对于凸块电极定位半导体芯片的电极焊盘的对准标记的布线板。

公开(公告)号：US20090011591A1

公开(公告)日：2009-01-08

申请号：US12230511

申请日：2008-08-29

Applicant: Hiroyuki Imamura

Inventor： Hiroyuki Imamura

IPC: H01L21/4763

CPC classification number: H05K1/189 ,  G02F1/13452 ,  H01L23/4985 ,  H01L24/29 ,  H01L24/83 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/2929 ,  H01L2224/293 ,  H01L2224/83101 ,  H01L2224/838 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/0781 ,  H01L2924/19043 ,  H05K1/0263 ,  H05K1/0265 ,  H05K1/0281 ,  H05K1/111 ,  H05K1/117 ,  H05K3/0097 ,  H05K3/108 ,  H05K3/243 ,  H05K3/361 ,  H05K2201/056 ,  H05K2201/09063 ,  H05K2201/09736 ,  H05K2201/09781 ,  H05K2201/10128 ,  H05K2201/10674 ,  H05K2201/10681 ,  H05K2201/2009 ,  H05K2203/0574 ,  H01L2224/29099 ,  H01L2224/29199 ,  H01L2224/29299 ,  H01L2224/05599

Abstract: In a film substrate (FB) including a film base material (1) and conductor wiring (23) that is formed on the film base material (1), the conductor wiring (23) is arranged such that the conductor wiring thickness of an external connection portion on the film substrate to which another panel or substrate is connected is thicker than the conductor wiring thickness of conductor wiring portions (bent portions) (25) at other positions.

Abstract translation: 在薄膜基材（1）和形成在薄膜基材（1）上的导体布线（23）的薄膜基板（FB）中，导体布线（23）布置成使外部的导体布线厚度 连接另一面板或基板的薄膜基板上的连接部分比其他位置的导体布线部分（弯曲部分）（25）的导体布线厚度厚。

公开(公告)号：US07425766B2

公开(公告)日：2008-09-16

申请号：US11043946

申请日：2005-01-28

Applicant: Hiroyuki Imamura

Inventor： Hiroyuki Imamura

IPC: H01L23/12 ,  G02F1/1345

CPC classification number: H05K1/189 ,  G02F1/13452 ,  H01L23/4985 ,  H01L24/29 ,  H01L24/83 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/2929 ,  H01L2224/293 ,  H01L2224/83101 ,  H01L2224/838 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/0781 ,  H01L2924/19043 ,  H05K1/0263 ,  H05K1/0265 ,  H05K1/0281 ,  H05K1/111 ,  H05K1/117 ,  H05K3/0097 ,  H05K3/108 ,  H05K3/243 ,  H05K3/361 ,  H05K2201/056 ,  H05K2201/09063 ,  H05K2201/09736 ,  H05K2201/09781 ,  H05K2201/10128 ,  H05K2201/10674 ,  H05K2201/10681 ,  H05K2201/2009 ,  H05K2203/0574 ,  H01L2224/29099 ,  H01L2224/29199 ,  H01L2224/29299 ,  H01L2224/05599

Abstract: In a film substrate (FB) including a film base material (1) and conductor wiring (23) that is formed on the film base material (1), the conductor wiring (23) is arranged such that the conductor wiring thickness of an external connection portion on the film substrate to which another panel or substrate is connected is thicker than the conductor wiring thickness of conductor wiring portions (bent portions) (25) at other positions.

Abstract translation: 在薄膜基材（1）和形成在薄膜基材（1）上的导体布线（23）的薄膜基板（FB）中，导体布线（23）布置成使外部的导体布线厚度 连接另一面板或基板的薄膜基板上的连接部分比其他位置的导体布线部分（弯曲部分）（25）的导体布线厚度厚。

公开(公告)号：US07294532B2

公开(公告)日：2007-11-13

申请号：US11146610

申请日：2005-06-07

Applicant: Hiroyuki Imamura ,  Nobuyuki Koutani

Inventor： Hiroyuki Imamura ,  Nobuyuki Koutani

IPC: H01L21/44

CPC classification number: H01L21/4853 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/4985 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/83192 ,  H01L2924/00014 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/3025 ,  H05K1/111 ,  H05K3/243 ,  H05K2201/0367 ,  H05K2201/09727 ,  H05K2201/098 ,  H05K2201/0989 ,  H05K2201/10674 ,  Y02P70/611 ,  H01L2924/00 ,  H01L2224/05599

Abstract: A method for manufacturing a semiconductor device that includes mounting a semiconductor chip on a circuit board having an insulating substrate, a plurality of wiring layers arranged on the insulating substrate, and bumps formed on the wiring layers respectively, in which the bump is provided across a longitudinal direction of a corresponding one of the wiring layers so as to extend over regions on both sides of the wiring layer and contact a surface of the insulating substrate, without a stepped portion formed on a surface of the bump, and a cross sectional shape of the bump taken in a width direction of the wiring layer is such that a central portion is higher than both side portions. The method also includes connecting electrode pads of the semiconductor chip to the bumps, thereby achieving connection between the electrode pads of the semiconductor chip and the wiring layers via the bumps.

Abstract translation: 一种半导体器件的制造方法，其包括将半导体芯片安装在具有绝缘基板的电路板上，布置在所述绝缘基板上的多个布线层以及分别形成在所述布线层上的凸块， 相对应的一个布线层的纵向方向延伸到布线层的两侧的区域上并与绝缘基板的表面接触，而不形成在凸起的表面上的阶梯部分，并且横截面形状 在布线层的宽度方向上取得的隆起部使得中央部高于两侧部。 该方法还包括将半导体芯片的电极焊盘连接到凸块，从而通过凸块实现半导体芯片的电极焊盘与布线层之间的连接。

公开(公告)号：US5219055A

公开(公告)日：1993-06-15

申请号：US900948

申请日：1992-06-17

Applicant: Hiroyuki Imamura

Inventor： Hiroyuki Imamura

IPC: F16H61/14

CPC classification number: F16H61/143 ,  Y10T477/635

Abstract: A spool of a lock-up control valve has a first effective area exposed to a release pressure which is supplied to a release chamber of the lock-up clutch and a second larger effective area which is exposed to the apply pressure which is supplied to an apply chamber. When acceleration is demanded when the lock-up clutch is in one of slip or fully lock-up modes and a sudden demand for acceleration is made, the pressure differential between the apply and release pressures is reduced below the normal level for a predetermined period of time.

Abstract translation: 锁定控制阀的阀芯具有暴露于释放压力的第一有效区域，该有效区域被供应到锁止离合器的释放室，并且暴露于施加压力的第二较大有效区域，该有效区域被供应到 应用室。 当锁止离合器处于滑动或完全锁定模式之一并且急剧加速的需求时需要加速时，施加和释放压力之间的压力差降低到正常水平以下一段预定时间 时间。

公开(公告)号：US20100309646A1

公开(公告)日：2010-12-09

申请号：US12440179

申请日：2007-10-17

Applicant: Makoto Morikawa ,  Tetsushi Tamura ,  Kenji Ueda ,  Hiroyuki Imamura

Inventor： Makoto Morikawa ,  Tetsushi Tamura ,  Kenji Ueda ,  Hiroyuki Imamura

IPC: F21V9/16 ,  F21V7/00 ,  F21V7/06

CPC classification number: F21S6/002 ,  F21K9/62 ,  F21K9/64 ,  F21K9/68 ,  F21S6/004 ,  F21S8/00 ,  F21V7/041 ,  F21Y2115/10 ,  H01L25/0753 ,  H01L33/60 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A light-emitting device (1) includes a base (10), a light reflecting member (11) placed on the base (10), a case (12) surrounding the light reflecting member (11), and a plurality of light-emitting elements (13) arranged on the inner surface of the case (12). The light reflecting member (11) reflects light emitted from an emission source including the light-emitting elements (13) toward an opening (12a) of the case (12). In the light-emitting device (1), since a plurality of light-emitting elements (13) can be arranged three-dimensionally, the size of the light-emitting device can be reduced easily. Moreover, the light reflecting member (11) reflects light emitted from the emission source including the light-emitting elements (13) toward the opening (12a) of the case (12), so that the light-emitting device can have high brightness.

Abstract translation: 发光装置（1）包括基座（10），放置在基座（10）上的光反射部件（11），围绕光反射部件（11）的壳体（12） 布置在壳体（12）的内表面上的发光元件（13）。 光反射部件（11）将包括发光元件（13）的发光源的光朝向壳体（12）的开口（12a）反射。 在发光装置（1）中，由于可以三维地配置多个发光元件（13），所以能够容易地减小发光装置的尺寸。 此外，光反射部件（11）将从包含发光元件（13）的发光源射出的光朝向壳体（12）的开口部（12a）反射，使得发光元件能够具有高亮度。

公开(公告)号：US20080173477A1

公开(公告)日：2008-07-24

申请号：US11901371

申请日：2007-09-17

Applicant: Hiroyuki Imamura ,  Nobuyuki Koutani

Inventor： Hiroyuki Imamura ,  Nobuyuki Koutani

IPC: H01L23/48

CPC classification number: H01L21/4853 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/4985 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/83192 ,  H01L2924/00014 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/3025 ,  H05K1/111 ,  H05K3/243 ,  H05K2201/0367 ,  H05K2201/09727 ,  H05K2201/098 ,  H05K2201/0989 ,  H05K2201/10674 ,  Y02P70/611 ,  H01L2924/00 ,  H01L2224/05599

Abstract: A circuit board includes a film substrate, a plurality of wiring layers arranged in order on the film substrate, and bumps formed on the wiring layers, respectively. Each of the bumps is provided across a longitudinal direction of a corresponding one of the wiring layers so as to extend over regions on both sides of the wiring layer above the insulating substrate, and a cross sectional shape of the bump taken in the width direction of the wiring layer is such that a central portion is higher than portions on both sides of the central portion. Accordingly, the bumps formed on the wiring layers can be held with strength sufficient for practical use against the force applied in the lateral direction.

Abstract translation: 电路板包括薄膜基板，在薄膜基板上依次布置的多个布线层和分别形成在布线层上的凸起。 每个凸块跨越相应的一个布线层的纵向方向设置，以便在绝缘基板上方的布线层的两侧的区域上延伸，并且沿宽度方向的凸起的横截面形状 布线层的中心部分高​​于中央部分两侧的部分。 因此，形成在布线层上的突起可以抵抗在横向施加的力而实际使用的强度。

公开(公告)号：US20050218496A1

公开(公告)日：2005-10-06

申请号：US11146802

申请日：2005-06-07

Applicant: Hiroyuki Imamura ,  Nobuyuki Koutani

Inventor： Hiroyuki Imamura ,  Nobuyuki Koutani

IPC: H05K3/34 ,  H01L21/48 ,  H01L21/60 ,  H01L23/495 ,  H01L23/498 ,  H05K1/02 ,  H05K1/11 ,  H05K3/24

CPC classification number: H01L21/4853 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/4985 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/83192 ,  H01L2924/00014 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/3025 ,  H05K1/111 ,  H05K3/243 ,  H05K2201/0367 ,  H05K2201/09727 ,  H05K2201/098 ,  H05K2201/0989 ,  H05K2201/10674 ,  Y02P70/611 ,  H01L2924/00 ,  H01L2224/05599

Abstract: A circuit board includes a film substrate, a plurality of wiring layers arranged in order on the film substrate, and bumps formed on the wiring layers, respectively. Each of the bumps is provided across a longitudinal direction of a corresponding one of the wiring layers so as to extend over regions on both sides of the wiring layer above the insulating substrate, and a cross sectional shape of the bump taken in the width direction of the wiring layer is such that a central portion is higher than portions on both sides of the central portion. Accordingly, the bumps formed on the wiring layers can be held with strength sufficient for practical use against the force applied in the lateral direction.

Abstract translation: 电路板包括薄膜基板，在薄膜基板上依次布置的多个布线层和分别形成在布线层上的凸起。 每个凸块跨越相应的一个布线层的纵向方向设置，以便在绝缘基板上方的布线层的两侧的区域上延伸，并且沿宽度方向的凸起的横截面形状 布线层的中心部分高​​于中央部分两侧的部分。 因此，形成在布线层上的突起可以抵抗在横向施加的力而实际使用的强度。

公开(公告)号：US06634875B2

公开(公告)日：2003-10-21

申请号：US10099970

申请日：2002-03-19

Applicant: Hiroyuki Imamura ,  Kazuo Sakurai ,  Keiji Tanaka ,  Yasuro Ohishi ,  Kiyoshi Fukatsu ,  Motoshi Hayashi ,  Shinya Nakamura ,  Akira Takenaka

Inventor： Hiroyuki Imamura ,  Kazuo Sakurai ,  Keiji Tanaka ,  Yasuro Ohishi ,  Kiyoshi Fukatsu ,  Motoshi Hayashi ,  Shinya Nakamura ,  Akira Takenaka

IPC: F04C1804

CPC classification number: F01C17/066

Abstract: An improved scroll compressor comprises a fixed scroll and an orbiting scroll, as well as an Oldham's coupling which enables the orbiting scroll to have a orbital movement. The Oldham's ring of the Oldham's coupling is so formed that its sliding surfaces for counterpart members to slide thereon are formed by a base material containing silicon particles, while the surface of each silicon particle (remaining on the base material's surface serving as a slidable surface for counterpart members to slide thereon) is formed into a flat surface. In practice, a ratio of silicon portions formed into flat surfaces to an entire sliding area of the Oldham's coupling is in a range of 3% to 20%, preferably 5% to 15%. With the use of the scroll compressor of the present invention, it is possible to improve the wear resistance of the Oldham's ring of the Oldham's coupling and its counterpart members in the scroll compressor.

Abstract translation: 改进的涡旋压缩机包括固定涡旋件和绕动涡旋件，以及使轨道运转涡旋件具有轨道运动的奥尔德姆联轴器。 奥尔德姆的十字形联轴节的环形被形成为使得其对准部件滑动的滑动表面由含有硅颗粒的基材形成，而每个硅颗粒的表面（保留在基材表面上用作可滑动表面， 在其上滑动的对方构件）形成为平坦表面。 在实践中，形成平坦表面的硅部分与奥尔德姆耦合的整个滑动区域的比率在3％至20％的范围内，优选为5％至15％。 通过使用本发明的涡旋压缩机，可以提高奥尔德姆联轴器的奥德姆环和涡旋压缩机中的对应构件的耐磨性。

公开(公告)号：US5152386A

公开(公告)日：1992-10-06

申请号：US578200

申请日：1990-09-06

Applicant: Hiroyuki Imamura

Inventor： Hiroyuki Imamura

IPC: F16H61/14

CPC classification number: F16H61/143 ,  Y10T477/635 ,  Y10T477/73

Abstract: A spool of a lock-up control valve has a first effective area exposed to a release pressure which is supplied to a release chamber of the lock-up clutch and a second larger effective area which is exposed to the apply pressure which is supplied to an apply chamber. When acceleration is demanded when the lock-up clutch is in one of slip or fully lock-up modes and a sudden demand for acceleration is made, the pressure differential between the apply and release pressures is reduced below the normal level for a predetermined period of time.

Abstract translation: 锁定控制阀的阀芯具有暴露于释放压力的第一有效区域，该有效区域被供应到锁止离合器的释放室，并且暴露于施加压力的第二较大有效区域，该有效区域被供应到 应用室。 当锁止离合器处于滑动或完全锁定模式之一并且急剧加速的需求时需要加速时，施加和释放压力之间的压力差降低到正常水平以下一段预定时间 时间。