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1.发明授权Configurable cascading sigma delta analog-to digital converter (ADC) for adjusting power and performance 有权可配置的级联Σ-Δ模数转换器（ADC），用于调节功率和性能公开(公告)号：US08421660B1
公开(公告)日：2013-04-16
申请号：US13304526
申请日：2011-11-25
IPC分类号： H03M3/00
摘要： A cascaded sigma-delta modulator has several modulator loops that have one or two sets of integrators, summers, and scalers, and a quantizer that generates a loop output. Input muxes to each loop select either an overall input or the loop output from a prior loop, allowing the modulator loops to be cascaded in series or to operate separately. Filter-configuring muxes after each modulator loop select either that loop's output or a loop output from any prior loop, or a zero. Each filter-configuring mux drives an input to a modified CIC filter. The modified CIC filter has an initial delay stage that receives the first filter-configuring mux output, and successive integrator stages that each receives a successive filter-configuring mux output. The modified CIC filter is a combination of a digital transform filter and a Cascaded-Integrator-Comb (CIC) filter. Modulator loops are powered down for lower-performance configurations or cascaded together for higher-performance configurations.
摘要翻译： 级联的Σ-Δ调制器具有多个调制器环路，其具有一组或两组积分器，加法器和定标器，以及产生回路输出的量化器。 对每个环路输入多路复用器，从一个先前的循环中选择一个总体输入或一个环路输出，使调制器回路串联级联或单独运行。 在每个调制器环路之后，滤波器配置的多路复用器选择该环路的输出或来自任何先前循环的回路输出或零。 每个过滤器配置的多路复用器驱动输入到修改后的CIC过滤器。 修改的CIC滤波器具有接收第一滤波器配置多路复用器输出的初始延迟级，以及每个接收连续的滤波器配置多路复用器输出的连续积分器级。 改进的CIC滤波器是数字变换滤波器和级联积分器（CIC） - 滤波器（Cascaded-Integrator-Comb，CIC）滤波器的组合。 调制解调器环路已经掉电，用于低性能配置或级联在一起以实现更高性能的配置。
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2.发明申请MULTI-STAGE COMPARATOR WITH OFFSET CANCELING CAPACITOR ACROSS SECONDARY DIFFERENTIAL INPUTS FOR HIGH-SPEED LOW-GAIN COMPARE AND HIGH-GAIN AUTO-ZEROING 有权具有偏移取消电容器的多级比较器，用于高速低增益比较和高增益自动调零的二次差分输入公开(公告)号：US20100164770A1
公开(公告)日：2010-07-01
申请号：US12347113
申请日：2008-12-31
CPC分类号： H03F3/005 , H03F3/45183 , H03F2200/375 , H03F2200/555 , H03F2203/45536 , H03F2203/45544 , H03F2203/45586 , H03F2203/45616 , H03F2203/45631 , H03F2203/45678 , H03F2203/45702 , H03F2203/45726 , H03F2203/45732 , H03M1/0607 , H03M1/0682 , H03M1/46
摘要： An Analog-to-Digital Converter (ADC) has a Successive-Approximation-Register (SAR) driving a digital-to-analog converter (DAC) that generates an analog voltage compared to an input voltage by a series of stages. The last stage feeds a compare signal to the SAR. Each stage has a dual-input differential amplifier that operates as a unity gain op amp during an auto-zeroing phase and as a high-speed low-gain amplifier during an amplifying phase. The dual-input differential amplifier has two pairs of differential inputs. A secondary pair has an offset-storing capacitor across it, and connects to the output pair through feedback switches during auto-zeroing. A primary pair connects to stage inputs through input switches during the amplifying phase. Since two pairs of differential inputs are provided to the dual-input differential amplifier, the offset capacitor is completely isolated from the input pair. The current sink in the dual-input differential amplifier is adjusted higher during the amplifying period.
摘要翻译： 模数转换器（ADC）具有驱动数模转换器（DAC）的逐次逼近寄存器（SAR），其通过一系列级与输入电压相比产生模拟电压。 最后一个阶段向SAR提供比较信号。 每个阶段都有一个双输入差分放大器，在自动归零阶段作为单位增益运算放大器工作，在放大阶段则作为高速低增益放大器工作。 双输入差分放大器有两对差分输入。 辅助对在其之间具有一个补偿存储电容器，并在自动归零期间通过反馈开关连接到输出对。 在放大阶段，初级对通过输入开关连接到级输入。 由于两对差分输入提供给双输入差分放大器，所以偏移电容与输入对完全隔离。 在放大期间，双输入差分放大器中的电流吸收器被调高。
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公开(公告)号：US08416107B1
公开(公告)日：2013-04-09
申请号：US13247119
申请日：2011-09-28
IPC分类号： H03M1/10
CPC分类号： H03M1/1033 , H03M1/0682 , H03M1/804
摘要： A calibrating Analog-to-Digital Converter (ADC) has an X-side array with binary-weighted capacitors that connect to an X-side line and a Y-side array connected to a Y-side line. Each array has binary-weighted capacitors from a most-significant-bit (MSB) to a least-significant-bit (LSB), but the LSB capacitor is duplicated as a termination capacitor and a middle capacitor between upper and lower groups is also duplicated as a surrogate capacitor. During calibration, lower array capacitors are switched low while the upper capacitors are driven by a thermometer-code value on both X and Y arrays. The thermometer value is inverted to the X-array but remains uninverted on the Y array. The lower array bits are tested to final a calibration value that has X and Y side voltages balanced.
摘要翻译： 校准模数转换器（ADC）具有X侧阵列，其具有连接到Y侧线的X侧线和Y侧阵列的二进制加权电容器。 每个阵列具有从最高有效位（MSB）到最低有效位（LSB）的二进制加权电容，但是LSB电容复制为终端电容，并且上下组之间的中间电容也被复制 作为替代电容器。 在校准期间，低阵列电容器切换低电平，而上电容器由X和Y阵列上的温度计代码值驱动。 温度计值反转到X阵列，但在Y阵列上保持不变。 测试较低的阵列位以最终确定平衡X和Y侧电压的校准值。
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4.发明授权Ultra low voltage multi-stage high-speed CMOS comparator with autozeroing 有权具有自动调零功能的超低压多级高速CMOS比较器公开(公告)号：US08258864B1
公开(公告)日：2012-09-04
申请号：US13238236
申请日：2011-09-21
申请人： Kwai Chi Chan , Yat To (William) Wong , Ho Ming (Karen) Wan , Kam Chuen Wan , Kwok Kuen (David) Kwong
发明人： Kwai Chi Chan , Yat To (William) Wong , Ho Ming (Karen) Wan , Kam Chuen Wan , Kwok Kuen (David) Kwong
IPC分类号： H03F1/02
CPC分类号： H03F3/45183 , H03F3/45636 , H03F2200/261 , H03F2200/294 , H03F2200/453 , H03F2203/45616 , H03F2203/45628
摘要： A pre-amplifier circuit can be cascaded and drive a latch for use in a precision analog-to-digital converter (ADC). The pre-amplifier has a main section and a feedback section connected by feedback resistors that do not produce voltage drops in the main section. Offset is stored on offset capacitors during an autozeroing phase and isolated by transmission gates during an amplifying phase. The offset capacitors drive the gates of feedback transistors that drive output nodes in the main section. Autozeroing sink transistors in the feedback section operate in the linear region while current sink transistors in the main section operate in the saturated region. Kickback-charge isolation transistors may be added for charge isolation. The output may also be equalized by an equalizing transmission gate. A very low power-supply voltage is supported even for high-speed operation with offset cancellation, due to the folded feedback resistor arrangement.
摘要翻译： 前级放大器电路可以级联并驱动锁存器，用于精密模数转换器（ADC）。 前置放大器有一个主要部分和一个反馈部分，通过反馈电阻连接，主部分不产生电压降。 偏移量在自动调零阶段存储在偏移电容上，并在放大阶段由传输门隔离。 偏移电容器驱动驱动主部分中的输出节点的反馈晶体管的栅极。 反馈部分中的自动归零陷波晶体管工作在线性区域，而主部分中的电流吸收晶体管工作在饱和区域。 可以添加Kickback电荷隔离晶体管用于电荷隔离。 输出也可以通过均衡的传输门来均衡。 由于折叠的反馈电阻器布置，即使对于具有偏移消除的高速操作也支持非常低的电源电压。
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5.发明授权Reduced residual offset sigma delta analog-to-digital converter (ADC) with chopper timing at end of integrating phase before trailing edge 有权减少残差偏移Σ-Δ模数转换器（ADC），在后沿积分相位结束时具有斩波定时公开(公告)号：US08471744B1
公开(公告)日：2013-06-25
申请号：US13308737
申请日：2011-12-01
IPC分类号： H03M3/00
摘要： An analog-to-digital converter (ADC) has a chopper-stabilized sigma-delta modulator (SDM). The SDM uses switched-capacitor integrators to sample, hold, and integrate an analog input in response to non-overlapping multi-phase clocks. Chopper multipliers are inserted on the inputs and outputs of an op amp in a first stage integrator. The chopper multipliers swap or pass through differential inputs in response to non-overlapping chopper clocks. A master clock operating at a frequency of the multi-phase clocks is divided down to trigger generation of the chopper clocks. Delay lines ensure that the edges of the chopper clocks occur before the edges of the multi-phase clocks. The chopper multipliers have already switched and are thus stable when multi-phase clocks change so charge injection at switches controlled by the multi-phase clocks is not immediately modulated by chopper multipliers. This clock timing increases the time available to respond to charge injection at switches improving linearity.
摘要翻译： 模数转换器（ADC）具有斩波稳定的Σ-Δ调制器（SDM）。 SDM使用开关电容积分器来采样，保持和集成模拟输入以响应不重叠的多相时钟。 斩波倍增器插入在第一级积分器中的运算放大器的输入和输出端。 斩波器乘法器响应于不重叠的斩波时钟交换或通过差分输入。 以多相时钟频率工作的主时钟被分频以触发斩波时钟的产生。 延迟线确保斩波时钟的边沿在多相时钟的边沿之前发生。 当多相时钟变化时，斩波倍增器已经切换并稳定，因此在由多相时钟控制的开关处的电荷注入不会被斩波乘法器立即调制。 该时钟定时增加了可以在改善线性度的开关处对电荷注入进行响应的时间。
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6.发明申请Slew-Rate-Enhanced Error Amp with Adaptive Transconductance and Single Dominant Pole Shared by Main and Auxiliary Amps 有权具有自适应跨导和主主导极共同的主要和辅助放大器的转换率增益误差放大器公开(公告)号：US20100164625A1
公开(公告)日：2010-07-01
申请号：US12345862
申请日：2008-12-30
申请人： Yat To (William) Wong , Chik Wai (David) Ng , Ho Ming (Karen) Wan , Kam Chuen Wan , Kwok Kuen (David) Kwong
发明人： Yat To (William) Wong , Chik Wai (David) Ng , Ho Ming (Karen) Wan , Kam Chuen Wan , Kwok Kuen (David) Kwong
IPC分类号： H03F3/45
CPC分类号： H03F3/45197 , H03F3/3023 , H03F3/45475 , H03F2203/45248 , H03F2203/45646 , H03F2203/45652 , H03F2203/45678
摘要： An error amplifier can be used to control a power regulator transistor. The error amplifier has a main amplifier, a pull-up auxiliary amplifier, and a pull-down auxiliary amplifier that all drive an output. A compensating capacitor on the output sets a single dominant pole for all amplifiers, increasing stability. High slew rates are provided by increased slew current from the auxiliary amplifiers that turn on when the differential input has an absolute voltage difference larger than an intentional offset. The intentional offset is introduced into the auxiliary amplifiers by adjusting a p-channel to n-channel transistor ratio in a leg of the auxiliary amplifiers. A source degenerated resistor in the main amplifier reduces supply headroom and increases linearity by connecting sources of two differential transistors that receive the differential input. Cascode transistors increase gain and output impedance. Reliability is increased as no positive feedback is used in the amplifiers.
摘要翻译： 误差放大器可用于控制功率调节晶体管。 误差放大器具有主放大器，上拉辅助放大器和全部驱动输出的下拉辅助放大器。 输出上的补偿电容为所有放大器设置单个主极，从而提高稳定性。 当差分输入具有大于有意偏移的绝对电压差时，来自辅助放大器的增加的转换电流提供高转换速率。 通过调整辅助放大器的一个支路中的p沟道至n沟道晶体管比，将有意的偏移引入辅助放大器。 主放大器中的源极退化电阻通过连接接收差分输入的两个差分晶体管的源极减小了供电余量并增加了线性度。 串联晶体管增加了增益和输出阻抗。 在放大器中没有使用正反馈的情况下，可靠性提高。
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7.发明申请ZERO-DELAY BUFFER WITH COMMON-MODE EQUALIZER FOR INPUT AND FEEDBACK DIFFERENTIAL CLOCKS INTO A PHASE-LOCKED LOOP (PLL) 有权具有用于输入和反馈差分时钟的共模均衡器的零延迟缓冲器进入相位锁定环路（PLL）公开(公告)号：US20090134923A1
公开(公告)日：2009-05-28
申请号：US11944545
申请日：2007-11-23
CPC分类号： H03L7/081 , H03L7/0891
摘要： A zero-delay clock generator has a phase-locked loop (PLL) that generates a feedback clock and receives a reference clocks. All clocks are differential and have a common-mode voltage. The common-mode voltage of an externally-generated reference clock can vary from the common-mode voltage of the internally-generated feedback clock. Differences in common-mode voltage of the reference clock and feedback clock cause delay variations resulting in static phase offsets of generated clocks. A common-mode sense and equalizer senses the common-mode voltages of the buffered reference and feedback clocks, and generates control voltages. The control voltages adjust the common-mode voltage and delay of differential buffers that receive the reference and feedback clocks. The control voltages adjust the differential buffers to match the common-mode voltages of the buffered reference and feedback clocks. The buffered clocks are then applied to a phase and frequency detector of the PLL.
摘要翻译： 零延迟时钟发生器具有产生反馈时钟并接收参考时钟的锁相环（PLL）。 所有时钟均为差分并具有共模电压。 外部产生的参考时钟的共模电压可以从内部产生的反馈时钟的共模电压变化。 参考时钟和反馈时钟的共模电压差异导致延迟变化，导致产生的时钟的静态相位偏移。 共模感测和均衡器感测缓冲参考和反馈时钟的共模电压，并产生控制电压。 控制电压调节接收参考和反馈时钟的差分缓冲器的共模电压和延迟。 控制电压调节差分缓冲器以匹配缓冲参考和反馈时钟的共模电压。 缓冲时钟然后被施加到PLL的相位和频率检测器。
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8.发明授权公开(公告)号：US08797776B2
公开(公告)日：2014-08-05
申请号：US13652474
申请日：2012-10-16
IPC分类号： H02M7/5387
CPC分类号： H02M7/219 , H02M2007/2195 , Y02B70/1408
摘要： A bridge rectifier operates on low A.C. input voltages such as received by a Radio-Frequency Identification (RFID) device. Voltage drops due to bridge diodes are avoided. Four p-channel transistors are arranged in a transistor bridge across the A.C. inputs to produce an internal power voltage. Another four diode-connected transistors form a start-up diode bridge that generates a comparator power voltage and a reference ground. The start-up diode bridge operates even during initial start-up before the comparator and boost drivers operate. A comparator receives the A.C. input and controls timing of voltage boost drivers that alternately drive gates of the four p-channel transistors in the transistor bridge with voltages boosted higher than the peak A.C. voltage. Substrates are connected to the power voltage on the power-voltage half of the bridge and to the A.C. inputs on the ground half of the bridge to fully shut off transistors, preventing reverse current flow.
摘要翻译： 桥式整流器在诸如由射频识别（RFID）设备接收的低交流输入电压下工作。 避免了由桥二极管引起的电压降。 四个P沟道晶体管布置在跨越交流输入的晶体管桥中以产生内部电源电压。 另外四个二极管连接的晶体管形成起始二极管电桥，产生比较器电源电压和参考地。 在比较器和升压驱动器运行之前，起动二极管桥即使在初始启动期间也工作。 比较器接收交流输入并且控制升压驱动器的定时，其交替地驱动晶体管桥中的四个p沟道晶体管的栅极，其电压升高高于峰值交流电压。 基板连接到桥的电源电压一半的电源电压和桥接器的一半的交流输入，以完全关闭晶体管，防止反向电流流动。
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9.发明申请Single-Power-Transistor Battery-Charging Circuit Using Voltage-Boosted Clock 有权使用电压升压时钟的单功率晶体管电池充电电路公开(公告)号：US20110267008A1
公开(公告)日：2011-11-03
申请号：US13179107
申请日：2011-07-08
申请人： Kwok Kuen Kwong , Yat To Wong , Ho Ming (Karen) Wan , Chik Wai Ng
发明人： Kwok Kuen Kwong , Yat To Wong , Ho Ming (Karen) Wan , Chik Wai Ng
IPC分类号： H02J7/00
CPC分类号： H02J7/0031
摘要： A charge/discharge protection circuit protects a battery from inadvertent shorting on a charger node that can connect to a charger or to a power supply of a portable electronic device. A single n-channel power transistor has a gate that controls a channel between the battery and the charger node. The gate is connected to the charger node by a gate-coupling transistor to turn off the power transistor, providing battery isolation. The gate is driven by a voltage-boosted clock through a switch activated by an enable signal. The enable signal also activates a grounding transistor to ground a gate of the gate-coupling transistor. A comparator compares voltages of the charger and battery nodes, and the compare output is latched to generate the enable signal. An inverse enable signal activates a second switch that drives the voltage-boosted clock to the gate of the gate-coupling transistor to turn off the power transistor.
摘要翻译： 充电/放电保护电路可保护电池免受可连接到充电器或便携式电子设备的电源的充电器节点上的意外短路。 单个n沟道功率晶体管具有控制电池和充电器节点之间的通道的栅极。 门通过栅极耦合晶体管连接到充电器节点，以关闭功率晶体管，从而提供电池隔离。 门通过由使能信号激活的开关由升压时钟驱动。 使能信号还激活接地晶体管以对栅极耦合晶体管的栅极接地。 比较器比较充电器和电池节点的电压，并且比较输出被锁存以产生使能信号。 反向使能信号激活第二开关，其将升压电压的时钟驱动到栅极耦合晶体管的栅极以截止功率晶体管。
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10.发明申请Single-Power-Transistor Battery-Charging Circuit Using Voltage-Boosted Clock 有权使用电压升压时钟的单功率晶体管电池充电电路公开(公告)号：US20100148727A1
公开(公告)日：2010-06-17
申请号：US12336514
申请日：2008-12-16
申请人： Kwok Kuen Kwong , Yat To Wong , Ho Ming (Karen) Wan , Chik Wai Ng
发明人： Kwok Kuen Kwong , Yat To Wong , Ho Ming (Karen) Wan , Chik Wai Ng
IPC分类号： H02J7/00
CPC分类号： H02J7/0031
摘要： A charge/discharge protection circuit protects a battery from inadvertent shorting on a charger node that can connect to a charger or to a power supply of a portable electronic device. A single n-channel power transistor has a gate that controls a channel between the battery and the charger node. The gate is connected to the charger node by a gate-coupling transistor to turn off the power transistor, providing battery isolation. The gate is driven by a voltage-boosted clock through a switch activated by an enable signal. The enable signal also activates a grounding transistor to ground a gate of the gate-coupling transistor. A comparator compares voltages of the charger and battery nodes, and the compare output is latched to generate the enable signal. An inverse enable signal activates a second switch that drives the voltage-boosted clock to the gate of the gate-coupling transistor to turn off the power transistor.
摘要翻译： 充电/放电保护电路可保护电池免受可连接到充电器或便携式电子设备的电源的充电器节点上的意外短路。 单个n沟道功率晶体管具有控制电池和充电器节点之间的通道的栅极。 门通过栅极耦合晶体管连接到充电器节点，以关闭功率晶体管，从而提供电池隔离。 门通过由使能信号激活的开关由升压时钟驱动。 使能信号还激活接地晶体管以对栅极耦合晶体管的栅极接地。 比较器比较充电器和电池节点的电压，并且比较输出被锁存以产生使能信号。 反向使能信号激活第二开关，其将升压电压的时钟驱动到栅极耦合晶体管的栅极，以关断功率晶体管。
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