公开(公告)号：US08504789B2

公开(公告)日：2013-08-06

申请号：US12823472

申请日：2010-06-25

申请人： Hong Beom Pyeon ,  Hunsam Jung ,  Peter B. Gillingham

发明人： Hong Beom Pyeon ,  Hunsam Jung ,  Peter B. Gillingham

IPC分类号： G06F12/00

CPC分类号： G06F1/08 ,  G06F3/0676 ,  G06F12/0246 ,  G06F13/1689 ,  G11C7/04

摘要： A composite memory device including discrete memory devices and a bridge device for controlling the discrete memory devices. A configurable clock controller receives a system clock and generates a memory clock having a frequency that is a predetermined ratio of the system clock. The system clock frequency is dynamically variable between a maximum and a minimum value, and the ratio of the memory clock frequency relative to the system clock frequency is set by loading a frequency register with a Frequency Divide Ratio (FDR) code any time during operation of the composite memory device. In response to the FDR code, the configurable clock controller changes the memory clock frequency.

摘要翻译： 一种复合存储器件，包括分立存储器件和用于控制分立存储器件的桥接器件。 可配置的时钟控制器接收系统时钟并产生具有系统时钟的预定比率的频率的存储器时钟。 系统时钟频率在最大和最小值之间动态变化，并且存储器时钟频率相对于系统时钟频率的比率通过在运行期间的任何时间加载具有频率分频比（FDR）代码的频率寄存器来设置 复合存储器件。 响应于FDR代码，可配置的时钟控制器改变存储器时钟频率。

公开(公告)号：US08549209B2

公开(公告)日：2013-10-01

申请号：US12508926

申请日：2009-07-24

申请人： Hong Beom Pyeon ,  Jin-Ki Kim ,  Peter B. Gillingham

发明人： Hong Beom Pyeon ,  Jin-Ki Kim ,  Peter B. Gillingham

IPC分类号： G06F13/00

CPC分类号： G06F12/0238 ,  G06F3/0634 ,  G06F12/04 ,  G06F12/0646 ,  G06F13/36 ,  G06F13/4234 ,  G06F13/4291 ,  G11C7/10 ,  G11C7/1006 ,  G11C7/1018 ,  G11C7/1039 ,  G11C7/106 ,  G11C7/1087

摘要： A composite memory device including discrete memory devices and a bridge device for controlling the discrete memory devices. The bridge device has memory organized as banks, where each bank is configured to have a virtual page size that is less than the maximum physical size of the page buffer. Therefore only a segment of data corresponding to the virtual page size stored in the page buffer is transferred to the bank. The virtual page size of the banks is provided in a virtual page size (VPS) configuration command having an ordered structure where the position of VPS data fields containing VPS configuration codes in the command correspond to different banks which are ordered from a least significant bank to a most significant bank. The VPS configuration command is variable in size, and includes only the VPS configuration codes for the highest significant bank being configured and the lower significant banks.

摘要翻译： 一种复合存储器件，包括分立存储器件和用于控制分立存储器件的桥接器件。 桥接器件具有组织为存储体的存储器，其中每个存储体被配置为具有小于页面缓冲器的最大物理大小的虚拟页面大小。 因此，只有与存储在页面缓冲器中的虚拟页大小相对应的数据段被传送到存储体。 以具有有序结构的虚拟页面大小（VPS）配置命令提供虚拟页面大小，其中在命令中包含VPS配置代码的VPS数据字段的位置对应于从最不重要的银行排序到不同的银行， 最重要的银行。 VPS配置命令的大小是可变的，并且只包括配置的最高有效存储库的VPS配置代码和较低的重要库。

公开(公告)号：US08812768B2

公开(公告)日：2014-08-19

申请号：US12033577

申请日：2008-02-19

申请人： Steven Przybylski ,  Roland Schuetz ,  HakJune Oh ,  Hong Beom Pyeon

发明人： Steven Przybylski ,  Roland Schuetz ,  HakJune Oh ,  Hong Beom Pyeon

IPC分类号： G06F12/00

CPC分类号： G06F3/0629 ,  G06F3/0604 ,  G06F3/0673 ,  G06F13/4243 ,  G06F13/4256 ,  G11C7/10 ,  G11C7/1042 ,  G11C7/20 ,  G11C8/06 ,  G11C8/10 ,  Y02D10/14 ,  Y02D10/151

摘要： A system having serially connected memory devices in a ring topology organization to realize high speed performance. The memory devices have dynamically configurable data widths such that the system can operate with up to a maximum common number of active data pads to maximize performance, or to operate with a single active data pad to minimize power consumption. Therefore the system can include a mix of memory devices having different data widths. The memory devices are dynamically configurable through the issuance of a single command propagated serially through all the memory devices from the memory controller in a broadcast operation. Robust operation of the system is ensured by implementing a data output inhibit algorithm, which prevents valid data from being provided to the memory controller when read output control signal is received out of its proper sequence.

摘要翻译： 一种在环形拓扑组织中具有串联连接的存储器件以实现高速性能的系统。 存储器件具有动态可配置的数据宽度，使得系统可以以高达最大公共数量的有源数据焊盘操作以最大化性能，或者使用单个有源数据焊盘操作以最小化功耗。 因此，系统可以包括具有不同数据宽度的存储器件的混合。 通过在广播操作中通过从存储器控制器的所有存储器装置串行传播的单个命令的发布来动态地配置存储器件。 通过实施数据输出禁止算法来确保系统的稳健运行，当从其正确的序列中接收到读取输出控制信号时，该算法防止有效数据被提供给存储器控制器。

公开(公告)号：US08526260B2

公开(公告)日：2013-09-03

申请号：US13305064

申请日：2011-11-28

申请人： Hong Beom Pyeon

发明人： Hong Beom Pyeon

IPC分类号： G11C7/00

CPC分类号： G11C11/4074 ,  G11C5/145 ,  G11C11/406 ,  G11C11/4076 ,  G11C2211/4061 ,  G11C2211/4067 ,  G11C2211/4068 ,  H02M3/073 ,  H02M2003/077

摘要： A dynamic random access memory (DRAM) is selectively operable in a sleep mode and another mode. The DRAM has data storage cells that are refreshed in the refresh mode. A boosted voltage is provided for the operation of the DRAM. A boosted voltage provider includes a group of charge pump circuits that are selectively activated by a pump control circuit based on a refresh time for refreshing data in the DRAM cells in the sleep mode.

公开(公告)号：US20130070547A1

公开(公告)日：2013-03-21

申请号：US13621486

申请日：2012-09-17

申请人： Hong Beom Pyeon

发明人： Hong Beom Pyeon

IPC分类号： G11C29/24

CPC分类号： G11C29/785 ,  G11C29/44 ,  G11C2029/1206 ,  G11C2029/4402

摘要： Systems and methods are disclosed that may include a first layer comprising a first redundant memory element, an input/output interface, a first layer fuse box, and a fuse blowing control. These systems and methods also may include a second layer coupled to the first layer through a first connection comprising a second layer memory element and a second layer fuse box coupled to the first redundant memory element. In addition, these systems and methods may further include a redundancy register coupled to the first layer, wherein upon the failure of part of the second layer memory element, the redundancy register provides information to the fuse blowing control that allocates part of the first redundant memory element to provide redundancy for the failed part of the second layer memory element by blowing elements in the first layer fuse box and the second layer fuse box.

摘要翻译： 公开了可以包括包括第一冗余存储器元件，输入/输出接口，第一层保险丝盒和保险丝熔断控制的第一层的系统和方法。 这些系统和方法还可以包括通过包括耦合到第一冗余存储器元件的第二层存储器元件和第二层熔丝盒的第一连接耦合到第一层的第二层。 此外，这些系统和方法还可以包括耦合到第一层的冗余寄存器，其中当第二层存储器元件的一部分出现故障时，冗余寄存器向熔丝熔断控制提供信息，其分配第一冗余存储器的一部分 元件，以通过在第一层熔丝盒和第二层熔丝盒中吹入元件来为第二层存储元件的故障部分提供冗余。

公开(公告)号：US08363444B2

公开(公告)日：2013-01-29

申请号：US13365895

申请日：2012-02-03

申请人： Jin-Ki Kim ,  HakJune Oh ,  Hong Beom Pyeon

发明人： Jin-Ki Kim ,  HakJune Oh ,  Hong Beom Pyeon

IPC分类号： G11C7/02

CPC分类号： G11C5/02 ,  G06F13/4234 ,  G06F13/4247 ,  G11C5/04 ,  G11C7/10 ,  G11C7/1003 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2924/15311

摘要： A bridge device architecture for connecting discrete memory devices. The bridge device is used in conjunction with a composite memory device including at least one discrete memory device. The bridge device includes a local control interface for connecting to the at least one discrete memory device, a local input/output interface for connecting to the at least one discrete memory device, and a global input/output interface. The global input/output interface receives and provides global memory control signals and also receives and provides write data to and read data from the at least one discrete memory device.

摘要翻译： 用于连接分立存储器件的桥接器件架构。 桥接器件与包括至少一个分立存储器件的复合存储器件结合使用。 桥接器件包括用于连接至少一个分立存储器件的本地控制接口，用于连接至少一个分立存储器件的本地输入/输出接口以及全局输入/输出接口。 全局输入/输出接口接收并提供全局存储器控制信号，并且还接收并向至少一个离散存储器件提供写入数据和从其读取数据。

公开(公告)号：US08300488B2

公开(公告)日：2012-10-30

申请号：US12705040

申请日：2010-02-12

申请人： Hong Beom Pyeon

发明人： Hong Beom Pyeon

IPC分类号： G11C7/00

CPC分类号： G11C11/406 ,  G11C7/04 ,  G11C11/40611 ,  G11C11/40615 ,  G11C11/40626 ,  G11C2211/4061

摘要： A dynamic random access memory (DRAM) device has an array of DRAM cells of rows by columns. Each DRAM cell of the array is coupled with a wordline of a corresponding row and a bitline of a corresponding column. An entry into and an exit from the self-refresh mode are detected by a mode detector and a self-refresh mode signal is provided. An oscillation circuit generates in response to the self-refresh mode signal generates a basic time period. A first frequency divider/time period multiplier changes the basic time period in accordance with a process variation factor relating to the DRAM device. A second frequency divider/time period multiplier further changes the changed time period in accordance with a temperature change factor relating to the DRAM device. In the self-refresh mode, data stored in the DRAM cells is refreshed. In accordance with the two factors, the DRAM devices perform and achieve reliable self-refresh for variable DRAM cell retention time.

摘要翻译： 动态随机存取存储器（DRAM）器件具有逐列的DRAM单元阵列。 阵列的每个DRAM单元与相应列的相应行和位线的字线相连。 通过模式检测器检测进入和退出自刷新模式，并提供自刷新模式信号。 响应于自刷新模式信号产生的振荡电路产生基本时间段。 第一分频器/时间周期乘法器根据与DRAM器件有关的过程变化因素来改变基本时间周期。 第二分频器/时间周期乘法器还根据与DRAM器件有关的温度变化因素来改变改变的时间周期。 在自刷新模式下，存储在DRAM单元中的数据被刷新。 根据这两个因素，DRAM器件执行并实现可变DRAM单元保留时间的可靠的自刷新。

公开(公告)号：US20120069693A1

公开(公告)日：2012-03-22

申请号：US13305064

申请日：2011-11-28

申请人： Hong Beom Pyeon

发明人： Hong Beom Pyeon

IPC分类号： G11C5/14

CPC分类号： G11C11/4074 ,  G11C5/145 ,  G11C11/406 ,  G11C11/4076 ,  G11C2211/4061 ,  G11C2211/4067 ,  G11C2211/4068 ,  H02M3/073 ,  H02M2003/077

摘要： A dynamic random access memory (DRAM) is selectively operable in a sleep mode and another mode. The DRAM has data storage cells that are refreshed in the refresh mode. A boosted voltage is provided for the operation of the DRAM. A boosted voltage provider includes a group of charge pump circuits that are selectively activated by a pump control circuit based on a refresh time for refreshing data in the DRAM cells in the sleep mode.

摘要翻译： 动态随机存取存储器（DRAM）可选择性地在睡眠模式和另一模式下操作。 DRAM具有在刷新模式下刷新的数据存储单元。 为DRAM的操作提供升压电压。 升压电压提供器包括一组电荷泵电路，其基于用于在睡眠模式下刷新DRAM单元中的数据的刷新时间由泵控制电路选择性地激活。

公开(公告)号：US08139414B2

公开(公告)日：2012-03-20

申请号：US13091479

申请日：2011-04-21

申请人： Jin-Ki Kim ,  Hong Beom Pyeon

发明人： Jin-Ki Kim ,  Hong Beom Pyeon

IPC分类号： G11C11/34

CPC分类号： G11C16/0483 ,  G11C16/08 ,  G11C16/10

摘要： A method for programming NAND flash cells to minimize program stress while allowing for random page programming operations. The method includes asymmetrically precharging a NAND string from a positively biased source line while the bitline is decoupled from the NAND string, followed by the application of a programming voltage to the selected memory cell, and then followed by the application of bitline data. After asymmetrical precharging and application of the programming voltage, all the selected memory cells will be set to a program inhibit state as they will be decoupled from the other memory cells in their respective NAND strings, and their channels will be locally boosted to a voltage effective for inhibiting programming. A VSS biased bitline will discharge the locally boosted channel to VSS, thereby allowing programming of the selected memory cell to occur. A VDD biased bitline will have no effect on the precharged NAND string, thereby maintaining a program inhibited state of that selected memory cell.

摘要翻译： 一种用于编程NAND闪存单元以最小化程序压力同时允许随机页面编程操作的方法。 该方法包括从正偏压的源极线不对称地预充电NAND串，同时位线与NAND串解耦，随后将编程电压施加到所选择的存储器单元，然后应用位线数据。 在非对称预充电和编程电压的施加之后，所有选定的存储单元将被设置为编程禁止状态，因为它们将与它们各自的NAND串中的其它存储单元分离，并且它们的通道将被局部升压到有效的电压 用于禁止编程。 VSS偏置位线将本地提升的通道放电到VSS，从而允许对所选存储单元进行编程。 VDD偏置位线对预充电NAND串不起作用，从而保持所选存储单元的程序禁止状态。

公开(公告)号：US20110317482A1

公开(公告)日：2011-12-29

申请号：US13110399

申请日：2011-05-18

申请人： Hong Beom Pyeon

发明人： Hong Beom Pyeon

IPC分类号： G11C11/00

CPC分类号： G11C13/0069 ,  G11C8/08 ,  G11C8/14 ,  G11C13/0004 ,  G11C13/0028 ,  G11C13/0038 ,  G11C13/004 ,  G11C2013/0071

摘要： A method for improving sub-word line response comprises generating a variable substrate bias determined by at least one user parameter. The variable substrate bias is applied to a sub-word line driver in a selected sub-block of a memory. A voltage disturbance on a sub-word line in communication with the sub-word line driver is minimized by modifying a variable substrate bias of the sub-word line driver to change a transconductance of the sub-word line driver thereby.

摘要翻译： 一种用于改善子字线响应的方法包括生成由至少一个用户参数确定的可变衬底偏置。 可变衬底偏置被施加到存储器的所选子块中的子字线驱动器。 通过修改子字线驱动器的可变衬底偏置来改变子字线驱动器的跨导，从而最小化与子字线驱动器通信的子字线上的电压干扰。