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公开(公告)号:US08471358B2
公开(公告)日:2013-06-25
申请号:US12791705
申请日:2010-06-01
申请人: Hsiao-Tsung Yen , Chin-Wei Kuo , Hsien-Pin Hu , Sally Liu , Ming-Fa Chen , Jhe-Ching Lu
发明人: Hsiao-Tsung Yen , Chin-Wei Kuo , Hsien-Pin Hu , Sally Liu , Ming-Fa Chen , Jhe-Ching Lu
IPC分类号: H01L27/08
CPC分类号: H01L23/5227 , H01F17/0013 , H01F27/2804 , H01L23/49822 , H01L2224/16225 , H01L2224/16227 , H01L2924/00014 , H01L2924/01322 , H01L2924/15311 , H01L2924/15321 , H01L2924/00 , H01L2224/0401
摘要: In accordance with an embodiment, a semiconductor device comprises a semiconductor die, an interposer, and conductive bumps bonding the semiconductor die to the interposer. The semiconductor die comprises a first metallization layer, and the first metallization layer comprises a first conductive pattern. The interposer comprises a second metallization layer, and the second metallization layer comprises a second conductive pattern. Some of the conductive bumps electrically couple the first conductive pattern to the second conductive pattern to form a coil. Other embodiments contemplate other configurations of coils, inductors, and/or transformers, and contemplate methods of manufacture.
摘要翻译: 根据实施例,半导体器件包括半导体管芯,插入件和将半导体管芯接合到插入件的导电凸块。 半导体管芯包括第一金属化层,第一金属化层包括第一导电图案。 插入器包括第二金属化层,并且第二金属化层包括第二导电图案。 一些导电凸块将第一导电图案电耦合到第二导电图案以形成线圈。 其他实施例考虑了线圈,电感器和/或变压器的其他配置,并考虑了制造方法。
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公开(公告)号:US08362591B2
公开(公告)日:2013-01-29
申请号:US12795734
申请日:2010-06-08
申请人: Hsiao-Tsung Yen , Hsien-Pin Hu , Jhe-Ching Lu , Chin-Wei Kuo , Ming-Fa Chen , Sally Liu
发明人: Hsiao-Tsung Yen , Hsien-Pin Hu , Jhe-Ching Lu , Chin-Wei Kuo , Ming-Fa Chen , Sally Liu
IPC分类号: H01L29/93
CPC分类号: H01L27/016 , H01L29/93
摘要: A three-dimensional integrated circuit includes a semiconductor substrate where the substrate has an opening extending through a first surface and a second surface of the substrate and where the first surface and the second surface are opposite surfaces of the substrate. A conductive material substantially fills the opening of the substrate to form a conductive through-substrate-via (TSV). An active circuit is disposed on the first surface of the substrate, an inductor is disposed on the second surface of the substrate and the TSV is electrically coupled to the active circuit and the inductor. The three-dimensional integrated circuit may include a varactor formed from a dielectric layer formed in the opening of the substrate such that the conductive material is disposed adjacent the dielectric layer and an impurity implanted region disposed surrounding the TSV such that the dielectric layer is formed between the impurity implanted region and the TSV.
摘要翻译: 三维集成电路包括半导体衬底,其中衬底具有延伸穿过衬底的第一表面和第二表面的开口,并且其中第一表面和第二表面是与衬底相对的表面。 导电材料基本上填充衬底的开口以形成导电的通过衬底通孔(TSV)。 有源电路设置在衬底的第一表面上,电感器设置在衬底的第二表面上,并且TSV电耦合到有源电路和电感器。 三维集成电路可以包括由形成在基板的开口中的电介质层形成的变容二极管,使得导电材料邻近介电层设置,以及设置在TSV周围的杂质注入区域,使得介电层形成在 杂质注入区和TSV。
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公开(公告)号:US20110291232A1
公开(公告)日:2011-12-01
申请号:US12791705
申请日:2010-06-01
申请人: Hsiao-Tsung Yen , Chin-Wei Kuo , Hsien-Pin Hu , Sally Liu , Ming-Fa Chen , Jhe-Ching Lu
发明人: Hsiao-Tsung Yen , Chin-Wei Kuo , Hsien-Pin Hu , Sally Liu , Ming-Fa Chen , Jhe-Ching Lu
CPC分类号: H01L23/5227 , H01F17/0013 , H01F27/2804 , H01L23/49822 , H01L2224/16225 , H01L2224/16227 , H01L2924/00014 , H01L2924/01322 , H01L2924/15311 , H01L2924/15321 , H01L2924/00 , H01L2224/0401
摘要: In accordance with an embodiment, a semiconductor device comprises a semiconductor die, an interposer, and conductive bumps bonding the semiconductor die to the interposer. The semiconductor die comprises a first metallization layer, and the first metallization layer comprises a first conductive pattern. The interposer comprises a second metallization layer, and the second metallization layer comprises a second conductive pattern. Some of the conductive bumps electrically couple the first conductive pattern to the second conductive pattern to form a coil. Other embodiments contemplate other configurations of coils, inductors, and/or transformers, and contemplate methods of manufacture.
摘要翻译: 根据实施例,半导体器件包括半导体管芯,插入件和将半导体管芯接合到插入件的导电凸块。 半导体管芯包括第一金属化层,第一金属化层包括第一导电图案。 插入器包括第二金属化层,并且第二金属化层包括第二导电图案。 一些导电凸块将第一导电图案电耦合到第二导电图案以形成线圈。 其他实施例考虑了线圈,电感器和/或变压器的其他配置,并考虑了制造方法。
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公开(公告)号:US08502338B2
公开(公告)日:2013-08-06
申请号:US12878803
申请日:2010-09-09
申请人: Hsiao-Tsung Yen , Hsien-Pin Hu , Chin-Wei Kuo , Sally Liu
发明人: Hsiao-Tsung Yen , Hsien-Pin Hu , Chin-Wei Kuo , Sally Liu
IPC分类号: H01L29/00
CPC分类号: H01L27/0296 , H01L21/76898 , H01L23/481 , H01L23/60 , H01L29/861 , H01L2223/6622 , H01L2224/13023 , H01L2224/13025 , H01L2224/13027 , H01L2224/131 , H01L2224/14181 , H01L2225/06513 , H01L2225/06541 , H01L2924/00014
摘要: A device includes a semiconductor substrate of a first conductivity type, wherein the semiconductor substrate comprises a first surface and a second surface opposite the first surface. A through-substrate via (TSV) extends from the first surface to the second surface of the semiconductor substrate. A well region of a second conductivity type opposite the first conductivity type encircles the TSV, and extends from the first surface to the second surface of the semiconductor substrate.
摘要翻译: 一种器件包括第一导电类型的半导体衬底,其中半导体衬底包括与第一表面相对的第一表面和第二表面。 贯穿基板通孔(TSV)从半导体基板的第一表面延伸到第二表面。 与第一导电类型相反的第二导电类型的阱区域包围TSV,并且从半导体衬底的第一表面延伸到第二表面。
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公开(公告)号:US20120061795A1
公开(公告)日:2012-03-15
申请号:US12878803
申请日:2010-09-09
申请人: Hsiao-Tsung Yen , Hsien-Pin Hu , Chin-Wei Kuo , Sally Liu
发明人: Hsiao-Tsung Yen , Hsien-Pin Hu , Chin-Wei Kuo , Sally Liu
IPC分类号: H01L29/92 , H01L21/265
CPC分类号: H01L27/0296 , H01L21/76898 , H01L23/481 , H01L23/60 , H01L29/861 , H01L2223/6622 , H01L2224/13023 , H01L2224/13025 , H01L2224/13027 , H01L2224/131 , H01L2224/14181 , H01L2225/06513 , H01L2225/06541 , H01L2924/00014
摘要: A device includes a semiconductor substrate of a first conductivity type, wherein the semiconductor substrate comprises a first surface and a second surface opposite the first surface. A through-substrate via (TSV) extends from the first surface to the second surface of the semiconductor substrate. A well region of a second conductivity type opposite the first conductivity type encircles the TSV, and extends from the first surface to the second surface of the semiconductor substrate.
摘要翻译: 一种器件包括第一导电类型的半导体衬底,其中半导体衬底包括与第一表面相对的第一表面和第二表面。 贯穿基板通孔(TSV)从半导体基板的第一表面延伸到第二表面。 与第一导电类型相反的第二导电类型的阱区域包围TSV,并且从半导体衬底的第一表面延伸到第二表面。
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公开(公告)号:US08674883B2
公开(公告)日:2014-03-18
申请号:US13114828
申请日:2011-05-24
申请人: Hsiao-Tsung Yen , Jhe-Ching Lu , Yu-Ling Lin , Chin-Wei Kuo , Min-Chie Jeng
发明人: Hsiao-Tsung Yen , Jhe-Ching Lu , Yu-Ling Lin , Chin-Wei Kuo , Min-Chie Jeng
IPC分类号: H01Q1/38
CPC分类号: H01Q1/50 , G06F17/5068 , H01L23/48 , H01L23/481 , H01L23/66 , H01L25/0657 , H01L25/074 , H01L2223/6616 , H01L2223/6677 , H01L2225/06531 , H01L2225/06541 , H01L2225/06548 , H01L2924/0002 , H01L2924/10253 , H01L2924/10272 , H01L2924/10329 , H01L2924/10333 , H01L2924/10335 , H01L2924/1421 , H01L2924/1461 , H01Q1/2283 , H01Q1/38 , H01Q5/357 , H01Q9/0421 , H01Q9/0442 , H01Q9/145 , Y10T29/49016 , H01L2924/00
摘要: An antenna includes a substrate and a top plate disposed over the substrate. At least one feed line is connected to the top plate, and each feed line comprises a first through-silicon via (TSV) structure passing through the substrate. At least one ground line is connected to the top plate, and each ground line comprises a second TSV structure passing through the substrate. The top plate is electrically conductive, and the at least one feed line is arranged to carry a radio frequency signal. The at least one ground line is arranged to be coupled to a ground.
摘要翻译: 天线包括衬底和设置在衬底上的顶板。 至少一个进料管线连接到顶板,并且每个进料管线包括穿过基材的第一穿硅通孔(TSV)结构。 至少一个接地线连接到顶板,并且每个接地线包括穿过衬底的第二TSV结构。 顶板是导电的,并且至少一个馈线布置成承载射频信号。 所述至少一个接地线被布置成联接到地面。
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公开(公告)号:US08502620B2
公开(公告)日:2013-08-06
申请号:US12944847
申请日:2010-11-12
申请人: Jhe-Ching Lu , Hsiao-Tsung Yen , Sally Liu , Tzu-Jin Yeh , Min-Chie Jeng
发明人: Jhe-Ching Lu , Hsiao-Tsung Yen , Sally Liu , Tzu-Jin Yeh , Min-Chie Jeng
CPC分类号: H01F21/12 , H01F27/2804 , H01F2027/2809 , H03H7/42 , Y10T29/49117
摘要: A system and method for transmitting signals is disclosed. An embodiment comprises a balun, such as a Marchand balun, which has a first transformer with a primary coil and a first secondary coil and a second transformer with the primary coil and a second secondary coil. The first secondary coil and the second secondary coil are connected to a ground plane, and the ground plane has slot lines located beneath the separation of the coils in the first transformer and the second transformer. The slot lines may also have fingers.
摘要翻译: 公开了一种用于发送信号的系统和方法。 一个实施例包括一个平衡 - 不平衡变换器,例如Marchand平衡 - 不平衡转换器,其具有带初级线圈的第一变压器和第一次级线圈,以及具有初级线圈的第二变压器和第二次级线圈。 第一次级线圈和第二次级线圈连接到接地平面,并且接地平面具有位于第一变压器和第二变压器中的线圈分离下方的槽线。 缝线也可以具有手指。
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公开(公告)号:US20120119845A1
公开(公告)日:2012-05-17
申请号:US12944847
申请日:2010-11-12
申请人: Jhe-Ching Lu , Hsiao-Tsung Yen , Sally Liu , Tzu-Jin Yeh , Min-Chie Jeng
发明人: Jhe-Ching Lu , Hsiao-Tsung Yen , Sally Liu , Tzu-Jin Yeh , Min-Chie Jeng
CPC分类号: H01F21/12 , H01F27/2804 , H01F2027/2809 , H03H7/42 , Y10T29/49117
摘要: A system and method for transmitting signals is disclosed. An embodiment comprises a balun, such as a Marchand balun, which has a first transformer with a primary coil and a first secondary coil and a second transformer with the primary coil and a second secondary coil. The first secondary coil and the second secondary coil are connected to a ground plane, and the ground plane has slot lines located beneath the separation of the coils in the first transformer and the second transformer. The slot lines may also have fingers.
摘要翻译: 公开了一种用于发送信号的系统和方法。 一个实施例包括一个平衡 - 不平衡变换器,例如Marchand平衡 - 不平衡转换器,其具有带初级线圈的第一变压器和第一次级线圈,以及具有初级线圈的第二变压器和第二次级线圈。 第一次级线圈和第二次级线圈连接到接地平面,并且接地平面具有位于第一变压器和第二变压器中的线圈分离下方的槽线。 缝线也可以具有手指。
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公开(公告)号:US08872345B2
公开(公告)日:2014-10-28
申请号:US13178079
申请日:2011-07-07
申请人: Chi-Chun Hsieh , Wei-Cheng Wu , Hsiao-Tsung Yen , Hsien-Pin Hu , Shang-Yun Hou , Shin-Puu Jeng
发明人: Chi-Chun Hsieh , Wei-Cheng Wu , Hsiao-Tsung Yen , Hsien-Pin Hu , Shang-Yun Hou , Shin-Puu Jeng
IPC分类号: H01L23/48 , H01L21/283 , H01L21/74
CPC分类号: H01L23/481 , H01L21/743 , H01L2924/0002 , H01L2924/00012 , H01L2924/00
摘要: A method of forming an interposer includes providing a semiconductor substrate, the semiconductor substrate having a front surface and a back surface opposite the front surface; forming one or more through-silicon vias (TSVs) extending from the front surface into the semiconductor substrate; forming an inter-layer dielectric (ILD) layer overlying the front surface of the semiconductor substrate and the one or more TSVs; and forming an interconnect structure in the ILD layer, the interconnect structure electrically connecting the one or more TSVs to the semiconductor substrate.
摘要翻译: 形成插入件的方法包括提供半导体衬底,该半导体衬底具有与前表面相对的前表面和后表面; 形成从所述前表面延伸到所述半导体衬底中的一个或多个穿硅通孔(TSV); 形成覆盖所述半导体衬底的前表面和所述一个或多个TSV的层间介电层(ILD)层; 以及在所述ILD层中形成互连结构,所述互连结构将所述一个或多个TSV电连接到所述半导体衬底。
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10.
公开(公告)号:US09087838B2
公开(公告)日:2015-07-21
申请号:US13280786
申请日:2011-10-25
申请人: Hsiao-Tsung Yen , Yu-Ling Lin , Chin-Wei Kuo , Ho-Hsiang Chen , Min-Chie Jeng
发明人: Hsiao-Tsung Yen , Yu-Ling Lin , Chin-Wei Kuo , Ho-Hsiang Chen , Min-Chie Jeng
IPC分类号: H01L23/52 , H01L21/02 , H01L23/522 , H01L23/64 , H01L49/02
CPC分类号: H01L23/5222 , H01F17/0013 , H01L21/76805 , H01L21/76877 , H01L23/5225 , H01L23/5227 , H01L23/528 , H01L23/552 , H01L23/642 , H01L23/645 , H01L28/10 , H01L2924/0002 , H01L2924/00
摘要: The present disclosure provides a semiconductor device. The semiconductor device includes a semiconductor substrate having an integrated circuit (IC) device; an interconnect structure disposed on the semiconductor substrate and coupled with the IC device; and a transformer disposed on the semiconductor substrate and integrated in the interconnect structure. The transformer includes a first conductive feature; a second conductive feature inductively coupled with the first conductive feature; a third conductive feature electrically connected to the first conductive feature; and a fourth conductive feature electrically connected to the second conductive feature. The third and fourth conductive features are designed and configured to be capacitively coupled to increase a coupling coefficient of the transformer.
摘要翻译: 本发明提供一种半导体器件。 半导体器件包括具有集成电路(IC)器件的半导体衬底; 布置在半导体衬底上并与IC器件耦合的互连结构; 以及设置在半导体衬底上并集成在互连结构中的变压器。 变压器包括第一导电特征; 与所述第一导电特征电感耦合的第二导电特征; 电连接到第一导电特征的第三导电特征; 以及电连接到第二导电特征的第四导电特征。 第三和第四导电特征被设计和配置为电容耦合以增加变压器的耦合系数。
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