公开(公告)号：US06802945B2

公开(公告)日：2004-10-12

申请号：US10336871

申请日：2003-01-06

申请人： Hsien-Tsung Liu ,  Chien-Kang Chou ,  Ching-San Lin

发明人： Hsien-Tsung Liu ,  Chien-Kang Chou ,  Ching-San Lin

IPC分类号： C23C1434

CPC分类号： C23C14/564 ,  C23C14/022 ,  H01L21/0206 ,  H01L21/2855 ,  H01L21/316 ,  H01L21/32051 ,  H01L24/11 ,  H01L2224/02126 ,  H01L2224/0231 ,  H01L2224/0401 ,  H01L2224/05166 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/1147 ,  H01L2224/13099 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01018 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01025 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/00014 ,  H01L2924/013

摘要： A method of forming a device, comprising the following steps. A wafer holder and inner walls of a chamber are coated with a seasoning layer The wafer is placed upon the wafer holder and is cleaned wherein a portion of the seasoning layer is re-deposited upon the wafer over and between adjacent wafer conductive structures. The wafer is removed from the chamber and at least two adjacent upper metal structures are formed over at least one portion of a metal barrier layer. The exposed portions of the metal barrier layer are etched and removed, exposing portions of the re-deposited seasoning layer portions using the metal barrier layer etch process which also removes any exposed portions of the re-deposited seasoning layer portions that are comprised of a material etchable in the metal barrier layer etch process.

摘要翻译： 一种形成装置的方法，包括以下步骤。 晶片保持器和腔室的内壁涂覆有调味剂层。晶片被放置在晶片保持器上并且被清洁，其中一部分调味剂层被重新沉积在晶片上并在相邻的晶片导电结构之间。 将晶片从腔室中取出，并且至少两个相邻的上部金属结构形成在金属阻挡层的至少一部分上。 蚀刻和去除金属阻挡层的暴露部分，使用金属阻挡层蚀刻工艺暴露重新沉积的调节层部分的部分，其还去除由材料构成的再沉积调理层部分的任何暴露部分 可在金属阻挡层蚀刻工艺中蚀刻。

公开(公告)号：US20060148247A1

公开(公告)日：2006-07-06

申请号：US11364375

申请日：2006-02-28

申请人： Hsien-Tsung Liu ,  Chien-Kang Chou ,  Ching-San Lin

发明人： Hsien-Tsung Liu ,  Chien-Kang Chou ,  Ching-San Lin

IPC分类号： H01L21/4763

CPC分类号： C23C14/564 ,  C23C14/022 ,  H01L21/0206 ,  H01L21/2855 ,  H01L21/316 ,  H01L21/32051 ,  H01L24/11 ,  H01L2224/02126 ,  H01L2224/0231 ,  H01L2224/0401 ,  H01L2224/05166 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/1147 ,  H01L2224/13099 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01018 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01025 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/00014 ,  H01L2924/013

摘要： A method of metal sputtering, comprising the following steps. A wafer holder and inner walls of a chamber are coated with a seasoning layer comprised of: a) a material etchable in a metal barrier layer etch process; or b) an insulating or non-conductive material. A wafer having two or more wafer conductive structures is placed upon the seasoning layer coated wafer holder. The wafer is cleaned wherein a portion of the seasoning layer is re-deposited upon the wafer over and between adjacent wafer conductive structures. A metal barrier layer is formed over the wafer. The wafer is removed from the chamber and at least two adjacent upper metal structures are formed over at least one portion of the metal barrier layer. The portions of the metal barrier layer not under the at least two adjacent upper metal structures are etched and removed from over the wafer exposing portions of the re-deposited seasoning layer portions using the metal barrier layer etch process which also removes any exposed portions of the re-deposited seasoning layer portions that are comprised of a material etchable in the metal barrier layer etch process.

摘要翻译： 一种金属溅射方法，包括以下步骤。 晶片保持器和室的内壁涂覆有调味层，调味层包括：a）可在金属阻挡层蚀刻工艺中蚀刻的材料; 或b）绝缘或非导电材料。 将具有两个或更多个晶片导电结构的晶片放置在调味层涂覆的晶片保持器上。 清洁晶片，其中一部分调味层在相邻的晶片导电结构之上和相邻的晶片导电结构之间重新沉积在晶片上。 在晶片上形成金属阻挡层。 将晶片从腔室中取出，并且在金属阻挡层的至少一部分上形成至少两个相邻的上部金属结构。 金属阻挡层不在至少两个相邻的上部金属结构之下的部分被蚀刻并从晶片的上方移除，使用金属阻挡层蚀刻工艺暴露部分再沉积的调节层部分，其也去除了 由金属阻挡层蚀刻工艺中可蚀刻的材料组成的再沉积的调味层部分。

公开(公告)号：US20050040033A1

公开(公告)日：2005-02-24

申请号：US10954781

申请日：2004-09-30

申请人： Hsien-Tsung Liu ,  Chien-Kang Chou ,  Ching-San Lin

发明人： Hsien-Tsung Liu ,  Chien-Kang Chou ,  Ching-San Lin

IPC分类号： C23C14/02 ,  C23C14/56 ,  H01L21/316 ,  H01L21/3205 ,  H01L21/60 ,  C23C14/32

CPC分类号： C23C14/564 ,  C23C14/022 ,  H01L21/0206 ,  H01L21/2855 ,  H01L21/316 ,  H01L21/32051 ,  H01L24/11 ,  H01L2224/02126 ,  H01L2224/0231 ,  H01L2224/0401 ,  H01L2224/05166 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/1147 ,  H01L2224/13099 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01018 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01025 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/00014 ,  H01L2924/013

摘要： A method of metal sputtering, comprising the following steps. A wafer holder and inner walls of a chamber are coated with a seasoning layer comprised of: a) a material etchable in a metal barrier layer etch process; or b) an insulating or non-conductive material. A wafer having two or more wafer conductive structures is placed upon the seasoning layer coated wafer holder. The wafer is cleaned wherein a portion of the seasoning layer is re-deposited upon the wafer over and between adjacent wafer conductive structures. A metal barrier layer is formed over the wafer. The wafer is removed from the chamber and at least two adjacent upper metal structures are formed over at least one portion of the metal barrier layer. The portions of the metal barrier layer not under the at least two adjacent upper metal structures are etched and removed from over the wafer exposing portions of the re-deposited seasoning layer portions using the metal barrier layer etch process which also removes any exposed portions of the re-deposited seasoning layer portions that are comprised of a material etchable in the metal barrier layer etch process.

摘要翻译： 一种金属溅射方法，包括以下步骤。 晶片保持器和室的内壁涂覆有调味层，调味层包括：a）可在金属阻挡层蚀刻工艺中蚀刻的材料; 或b）绝缘或非导电材料。 将具有两个或更多个晶片导电结构的晶片放置在调味层涂覆的晶片保持器上。 清洁晶片，其中一部分调味层在相邻的晶片导电结构之上和相邻的晶片导电结构之间重新沉积在晶片上。 在晶片上形成金属阻挡层。 将晶片从腔室中取出，并且在金属阻挡层的至少一部分上形成至少两个相邻的上部金属结构。 金属阻挡层不在至少两个相邻的上部金属结构之下的部分被蚀刻并从晶片的上方移除，使用金属阻挡层蚀刻工艺暴露部分再沉积的调节层部分，其也去除了 由金属阻挡层蚀刻工艺中可蚀刻的材料组成的再沉积的调味层部分。

公开(公告)号：US08723322B2

公开(公告)日：2014-05-13

申请号：US11364375

申请日：2006-02-28

申请人： Hsien-Tsung Liu ,  Chien-Kang Chou ,  Ching-San Lin

发明人： Hsien-Tsung Liu ,  Chien-Kang Chou ,  Ching-San Lin

IPC分类号： H01L23/48

CPC分类号： C23C14/564 ,  C23C14/022 ,  H01L21/0206 ,  H01L21/2855 ,  H01L21/316 ,  H01L21/32051 ,  H01L24/11 ,  H01L2224/02126 ,  H01L2224/0231 ,  H01L2224/0401 ,  H01L2224/05166 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/1147 ,  H01L2224/13099 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01018 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01025 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/00014 ,  H01L2924/013

摘要： A method of metal sputtering, comprising the following steps. A wafer holder and inner walls of a chamber are coated with a seasoning layer comprised of: a) a material etchable in a metal barrier layer etch process; or b) an insulating or non-conductive material. A wafer having two or more wafer conductive structures is placed upon the seasoning layer coated wafer holder. The wafer is cleaned wherein a portion of the seasoning layer is re-deposited upon the wafer over and between adjacent wafer conductive structures. A metal barrier layer is formed over the wafer. The wafer is removed from the chamber and at least two adjacent upper metal structures are formed over at least one portion of the metal barrier layer. The portions of the metal barrier layer not under the at least two adjacent upper metal structures are etched and removed from over the wafer exposing portions of the re-deposited seasoning layer portions using the metal barrier layer etch process which also removes any exposed portions of the re-deposited seasoning layer portions that are comprised of a material etchable in the metal barrier layer etch process.

摘要翻译： 一种金属溅射方法，包括以下步骤。 晶片保持器和室的内壁涂覆有调味层，调味层包括：a）可在金属阻挡层蚀刻工艺中蚀刻的材料; 或b）绝缘或非导电材料。 将具有两个或更多个晶片导电结构的晶片放置在调味层涂覆的晶片保持器上。 清洁晶片，其中一部分调味层在相邻的晶片导电结构之上和相邻的晶片导电结构之间重新沉积在晶片上。 在晶片上形成金属阻挡层。 将晶片从腔室中取出，并且在金属阻挡层的至少一部分上形成至少两个相邻的上部金属结构。 金属阻挡层不在至少两个相邻的上部金属结构之下的部分被蚀刻并从晶片的上方移除，使用金属阻挡层蚀刻工艺暴露部分再沉积的调节层部分，其也去除了 由金属阻挡层蚀刻工艺中可蚀刻的材料组成的再沉积的调味层部分。

公开(公告)号：US20090218687A1

公开(公告)日：2009-09-03

申请号：US12464896

申请日：2009-05-13

申请人： Chiu-Ming Chou ,  Chien-Kang Chou ,  Ching-San Lin ,  Mou-Shiung Lin

发明人： Chiu-Ming Chou ,  Chien-Kang Chou ,  Ching-San Lin ,  Mou-Shiung Lin

IPC分类号： H01L23/498

CPC分类号： H01L24/06 ,  H01L21/76801 ,  H01L24/12 ,  H01L2224/0401 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/01074 ,  H01L2924/01076 ,  H01L2924/01079 ,  H01L2924/05042 ,  H01L2924/10329 ,  H01L2924/14 ,  H01L2924/15788 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/00

摘要： The invention provides a semiconductor chip comprising a semiconductor substrate comprising a MOS device, an interconnecting structure over said semiconductor substrate, and a metal bump over said MOS device, wherein said metal bump has more than 50 percent by weight of gold and has a height of between 8 and 50 microns.

摘要翻译： 本发明提供一种半导体芯片，其包括半导体衬底，该半导体衬底包括MOS器件，在所述半导体衬底上的互连结构以及在所述MOS器件上方的金属凸块，其中所述金属凸块具有大于50重量％的金， 介于8和50微米之间。

公开(公告)号：US07547969B2

公开(公告)日：2009-06-16

申请号：US11262182

申请日：2005-10-28

申请人： Chiu-Ming Chou ,  Chien-Kang Chou ,  Ching-San Lin ,  Mou-Shiung Lin

发明人： Chiu-Ming Chou ,  Chien-Kang Chou ,  Ching-San Lin ,  Mou-Shiung Lin

IPC分类号： H01L23/48

CPC分类号： H01L24/06 ,  H01L21/76801 ,  H01L24/12 ,  H01L2224/0401 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/01074 ,  H01L2924/01076 ,  H01L2924/01079 ,  H01L2924/05042 ,  H01L2924/10329 ,  H01L2924/14 ,  H01L2924/15788 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/00

摘要： The invention provides a semiconductor chip comprising a semiconductor substrate comprising a MOS device, an interconnecting structure over said semiconductor substrate, and a metal bump over said MOS device, wherein said metal bump has more than 50 percent by weight of gold and has a height of between 8 and 50 microns.

摘要翻译： 本发明提供一种半导体芯片，其包括半导体衬底，该半导体衬底包括MOS器件，在所述半导体衬底上的互连结构以及在所述MOS器件上方的金属凸块，其中所述金属凸块具有大于50重量％的金， 介于8和50微米之间。

公开(公告)号：US20060091540A1

公开(公告)日：2006-05-04

申请号：US11262182

申请日：2005-10-28

申请人： Chiu-Ming Chou ,  Chien-Kang Chou ,  Ching-San Lin ,  Mou-Shiung Lin

发明人： Chiu-Ming Chou ,  Chien-Kang Chou ,  Ching-San Lin ,  Mou-Shiung Lin

IPC分类号： H01L23/48

CPC分类号： H01L24/06 ,  H01L21/76801 ,  H01L24/12 ,  H01L2224/0401 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/01074 ,  H01L2924/01076 ,  H01L2924/01079 ,  H01L2924/05042 ,  H01L2924/10329 ,  H01L2924/14 ,  H01L2924/15788 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/00

摘要： The invention provides a semiconductor chip comprising a semiconductor substrate comprising a MOS device, an interconnecting structure over said semiconductor substrate, and a metal bump over said MOS device, wherein said metal bump has more than 50 percent by weight of gold and has a height of between 8 and 50 microns.

摘要翻译： 本发明提供一种半导体芯片，其包括半导体衬底，该半导体衬底包括MOS器件，在所述半导体衬底上的互连结构以及在所述MOS器件上方的金属凸块，其中所述金属凸块具有大于50重量％的金， 介于8和50微米之间。

公开(公告)号：US08319354B2

公开(公告)日：2012-11-27

申请号：US13181255

申请日：2011-07-12

申请人： Mou-Shiung Lin ,  Hsin-Jung Lo ,  Chien-Kang Chou ,  Chiu-Ming Chou ,  Ching-San Lin

发明人： Mou-Shiung Lin ,  Hsin-Jung Lo ,  Chien-Kang Chou ,  Chiu-Ming Chou ,  Ching-San Lin

IPC分类号： H01L23/52 ,  H01L23/48 ,  H01L29/40

CPC分类号： H01L24/73 ,  H01L23/5329 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/0231 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/04073 ,  H01L2224/05155 ,  H01L2224/05173 ,  H01L2224/05176 ,  H01L2224/05553 ,  H01L2224/05572 ,  H01L2224/05599 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/05669 ,  H01L2224/05673 ,  H01L2224/05676 ,  H01L2224/1147 ,  H01L2224/131 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/13169 ,  H01L2224/13173 ,  H01L2224/13176 ,  H01L2224/48463 ,  H01L2224/48477 ,  H01L2224/4943 ,  H01L2224/85051 ,  H01L2224/85399 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01044 ,  H01L2924/01045 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01059 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/05042 ,  H01L2924/10329 ,  H01L2924/14 ,  H01L2924/15788 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2224/13099 ,  H01L2224/45099 ,  H01L2924/00 ,  H01L2224/4554

摘要： The invention provides a semiconductor chip comprising an interconnecting structure over said passivation layer. The interconnecting structure comprises a first contact pad connected to a second contact pad exposed by an opening in a passivation layer. A metal bump is on the first contact pad and over multiple semiconductor devices, wherein the metal bump has more than 50 percent by weight of gold and has a height of between 8 and 50 microns.

摘要翻译： 本发明提供一种包括在所述钝化层上的互连结构的半导体芯片。 互连结构包括连接到由钝化层中的开口暴露的第二接触焊盘的第一接触焊盘。 金属凸块位于第一接触焊盘上并在多个半导体器件上，其中金属凸块具有超过50重量％的金并且具有在8和50微米之间的高度。

公开(公告)号：US20070096313A1

公开(公告)日：2007-05-03

申请号：US11262184

申请日：2005-10-28

申请人： Chiu-Ming Chou ,  Chien-Kang Chou ,  Ching-San Lin ,  Mou-Shiung Lin ,  Hsin-Jung Lo

发明人： Chiu-Ming Chou ,  Chien-Kang Chou ,  Ching-San Lin ,  Mou-Shiung Lin ,  Hsin-Jung Lo

IPC分类号： H01L23/48 ,  H01L21/44 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L24/73 ,  H01L23/5329 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/0231 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/04073 ,  H01L2224/05155 ,  H01L2224/05173 ,  H01L2224/05176 ,  H01L2224/05553 ,  H01L2224/05572 ,  H01L2224/05599 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/05669 ,  H01L2224/05673 ,  H01L2224/05676 ,  H01L2224/1147 ,  H01L2224/131 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/13169 ,  H01L2224/13173 ,  H01L2224/13176 ,  H01L2224/48463 ,  H01L2224/48477 ,  H01L2224/4943 ,  H01L2224/85051 ,  H01L2224/85399 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01044 ,  H01L2924/01045 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01059 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/05042 ,  H01L2924/10329 ,  H01L2924/14 ,  H01L2924/15788 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2224/13099 ,  H01L2224/45099 ,  H01L2924/00 ,  H01L2224/4554

摘要： The invention provides a semiconductor chip comprising an interconnecting structure over said passivation layer. The interconnecting structure comprises a first contact pad connected to a second contact pad exposed by an opening in a passivation layer. A metal bump is on the first contact pad and over multiple semiconductor devices, wherein the metal bump has more than 50 percent by weight of gold and has a height of between 8 and 50 microns

摘要翻译： 本发明提供一种包括在所述钝化层上的互连结构的半导体芯片。 互连结构包括连接到由钝化层中的开口暴露的第二接触焊盘的第一接触焊盘。 金属凸块位于第一接触焊盘上并且在多个半导体器件上，其中金属凸块具有超过50重量％的金并且具有在8和50微米之间的高度

公开(公告)号：US08242601B2

公开(公告)日：2012-08-14

申请号：US12464896

申请日：2009-05-13

申请人： Chiu-Ming Chou ,  Chien-Kang Chou ,  Ching-San Lin ,  Mou-Shiung Lin

发明人： Chiu-Ming Chou ,  Chien-Kang Chou ,  Ching-San Lin ,  Mou-Shiung Lin

IPC分类号： H01L23/48

CPC分类号： H01L24/06 ,  H01L21/76801 ,  H01L24/12 ,  H01L2224/0401 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/01074 ,  H01L2924/01076 ,  H01L2924/01079 ,  H01L2924/05042 ,  H01L2924/10329 ,  H01L2924/14 ,  H01L2924/15788 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/00

摘要： The invention provides a semiconductor chip comprising a semiconductor substrate comprising a MOS device, an interconnecting structure over said semiconductor substrate, and a metal bump over said MOS device, wherein said metal bump has more than 50 percent by weight of gold and has a height of between 8 and 50 microns.

摘要翻译： 本发明提供一种半导体芯片，其包括半导体衬底，该半导体衬底包括MOS器件，在所述半导体衬底上的互连结构以及在所述MOS器件上方的金属凸块，其中所述金属凸块具有大于50重量％的金， 介于8和50微米之间。