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公开(公告)号:US08766438B2
公开(公告)日:2014-07-01
申请号:US13393459
申请日:2009-09-01
IPC分类号: H01L23/48
CPC分类号: H01L21/563 , H01L23/3171 , H01L23/3192 , H01L24/13 , H01L24/14 , H01L24/16 , H01L24/32 , H01L24/33 , H01L2224/02166 , H01L2224/0401 , H01L2224/04026 , H01L2224/05567 , H01L2224/05578 , H01L2224/056 , H01L2224/05687 , H01L2224/0569 , H01L2224/10125 , H01L2224/10126 , H01L2224/13008 , H01L2224/13012 , H01L2224/13016 , H01L2224/13027 , H01L2224/141 , H01L2224/14153 , H01L2224/16245 , H01L2224/26125 , H01L2224/73203 , H01L2224/73204 , H01L2924/00013 , H01L2924/00014 , H01L2924/0002 , H01L2924/01006 , H01L2924/014 , H01L2924/15788 , H01L2924/05442 , H01L2924/05042 , H01L2224/13099 , H01L2224/05099 , H01L2224/13599 , H01L2224/05599 , H01L2224/29099 , H01L2224/29599 , H01L2924/3512 , H01L2924/00 , H01L2224/05552 , H01L2924/00012
摘要: The invention discloses a package structure including a semiconductor device, a first protection layer, a second protection layer and at least one conductive connector. The semiconductor device has at least one pad. The first protection layer is disposed on the semiconductor device and exposes the pad. The second protection layer, disposed on the first protection layer, has at least one first opening and at least one second opening. The first opening exposes a partial surface of the pad. The second opening exposes a partial surface of the first protection layer. The conductive connector, opposite to the pad, is disposed on the second protection layer and coupled to the pad through the first openings.
摘要翻译: 本发明公开了一种包括半导体器件,第一保护层,第二保护层和至少一个导电连接器的封装结构。 半导体器件具有至少一个焊盘。 第一保护层设置在半导体器件上并使焊盘露出。 设置在第一保护层上的第二保护层具有至少一个第一开口和至少一个第二开口。 第一开口露出垫的部分表面。 第二开口露出第一保护层的部分表面。 与焊盘相对的导电连接器设置在第二保护层上,并通过第一开口与焊盘相连。
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公开(公告)号:US07456496B2
公开(公告)日:2008-11-25
申请号:US11128014
申请日:2005-05-12
申请人: Tan Kim Hwee , Roman Perez , Kee Kwang Lau , Alex Chew , Antonio Dimaano
发明人: Tan Kim Hwee , Roman Perez , Kee Kwang Lau , Alex Chew , Antonio Dimaano
CPC分类号: H01L23/36 , H01L21/568 , H01L23/3114 , H01L24/96 , H01L2224/05573 , H01L2224/12105 , H01L2224/16 , H01L2924/18162 , H01L2224/05647 , H01L2924/00014
摘要: A chip level package utilizing a CGA is described. A semiconductor chip with pillars is molded in an encapsulant. Solder balls are added and connected to the chip pillars. The final package does not require a first level substrate or interposer and is able to be assembled to the next level as is. An additional embodiment describes the addition of a thermal heat sink to the packaged chip.
摘要翻译: 描述了利用CGA的芯片级封装。 具有支柱的半导体芯片被模制在密封剂中。 焊球被添加并连接到芯片支柱。 最终包装不需要第一级基板或插入件,并且能够按原样组装到一个新的水平。 另外的实施例描述了将热散热器添加到封装芯片。
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公开(公告)号:US20060060937A1
公开(公告)日:2006-03-23
申请号:US10947910
申请日:2004-09-23
IPC分类号: H01L29/00
摘要: As the functionality, speed and portability of consumer electronics increases, so does the need for more circuitry to be packed into smaller spaces. All this leads to the fact that the size of a device is now becoming more often a function of the circuit board or module size than anything else. In order to achieve size reduction of multi-featured products, passive components on the surface of the circuit need to be eliminated by burying them within the inner layers of the printed wiring board. Embedded passives are passive components placed between the interconnecting substrates of a printed wiring board. Implementation of embedded passives reduces space requirements and enables more silicon devices to be placed on the same sized substrate, thereby allowing functional potential of small electronic devices to increase. However, additional steps are conventionally required for embedding passive components within the interconnect layer between substrates. An embodiment of the invention discloses an embedded passive component comprising electrically conductive pillars formed on a substrate. One portion of the pillars functions as a passive structure and another portion of the pillars functions as inter-displacement means. As only pillars are used, steps for forming the embedded passive component are simplified and quantitatively reduced.
摘要翻译: 随着消费电子产品的功能,速度和便携性的增加,更多电路的需求也将增加到更小的空间。 所有这一切导致一个事实,即现在,设备的尺寸通常是电路板或模块尺寸的函数。 为了实现多功能产品的尺寸减小,需要通过将电路掩埋在印刷电路板的内层内来消除电路表面上的无源部件。 嵌入式无源器件是放置在印刷电路板的互连衬底之间的无源部件。 嵌入式无源器件的实现减少了空间需求,并使更多的硅器件放置在相同尺寸的衬底上,从而允许小型电子器件的功能增加。 然而,传统上需要在衬底之间的互连层内嵌入无源部件的附加步骤。 本发明的实施例公开了一种嵌入式无源部件,其包括形成在基板上的导电柱。 柱的一部分用作被动结构,并且柱的另一部分用作位移间装置。 由于仅使用支柱,因此简化并定量降低了形成嵌入式无源元件的步骤。
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公开(公告)号:US06929981B2
公开(公告)日:2005-08-16
申请号:US10236337
申请日:2002-09-06
申请人: Tan Kim Hwee , Roman Perez , Kee Kwang Lau , Alex Chew , Antonio Dimaano
发明人: Tan Kim Hwee , Roman Perez , Kee Kwang Lau , Alex Chew , Antonio Dimaano
CPC分类号: H01L23/36 , H01L21/568 , H01L23/3114 , H01L24/96 , H01L2224/05573 , H01L2224/12105 , H01L2224/16 , H01L2924/18162 , H01L2224/05647 , H01L2924/00014
摘要: A chip level package utilizing a CGA is described. A semiconductor chip with pillars is molded in an encapsulant. Solder balls are added and connected to the chip pillars. The final package does not require a first level substrate or interposer and is able to be assembled to the next level as is. An additional embodiment describes the addition of a thermal heat sink to the packaged chip.
摘要翻译: 描述了利用CGA的芯片级封装。 具有支柱的半导体芯片被模制在密封剂中。 焊球被添加并连接到芯片支柱。 最终包装不需要第一级基板或插入件,并且能够按原样组装到一个新的水平。 另外的实施例描述了将热散热器添加到封装芯片。
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公开(公告)号:US06734039B2
公开(公告)日:2004-05-11
申请号:US10236385
申请日:2002-09-06
申请人: Tan Kim Hwee , Roman Perez , Kee Kwang Lau , Alex Chew , Antonio Dimaano
发明人: Tan Kim Hwee , Roman Perez , Kee Kwang Lau , Alex Chew , Antonio Dimaano
IPC分类号: H01L2144
CPC分类号: H01L21/6835 , H01L21/565 , H01L21/568 , H01L23/3114 , H01L24/11 , H01L24/12 , H01L2224/05573 , H01L2224/1147 , H01L2224/1308 , H01L2224/13082 , H01L2224/131 , H01L2224/13111 , H01L2224/13147 , H01L2924/00013 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01076 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , H01L2924/15311 , H01L2924/15747 , H01L2924/181 , H05K3/3436 , H05K3/3452 , H05K2201/09045 , Y02P70/613 , H01L2924/00014 , H01L2224/13099 , H01L2924/00 , H01L2224/05647
摘要: A chip level package utilizing a CGA is described. A semiconductor chip with pillars is molded in an encapsulant. Solder balls are added and connected to the chip pillars. The final package does not require a first level substrate or interposer and is able to be assembled to the next level as is.
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