公开(公告)号：US20140167270A1

公开(公告)日：2014-06-19

申请号：US13716017

申请日：2012-12-14

Applicant: INFINEON TECHNOLOGIES AG

Inventor： Paul Ganitzer ,  Kurt Matoy ,  Martin Sporn ,  Mark Harrison

IPC: H01L23/498 ,  H01L21/02

CPC classification number: H01L23/49866 ,  H01L21/02697 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L24/29 ,  H01L2224/0347 ,  H01L2224/03848 ,  H01L2224/0401 ,  H01L2224/04026 ,  H01L2224/05083 ,  H01L2224/05124 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05172 ,  H01L2224/05639 ,  H01L2224/13111 ,  H01L2224/29111 ,  H01L2924/0002 ,  H01L2924/10253 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/01023

Abstract: In one embodiment method, a first Ti based layer is deposited on the substrate. An intermediate Al based layer is deposited on the first layer, a second NiV based layer is deposited on the intermediate layer, and a third Ag based layer is deposited on the second layer. The layer stack is tempered in such a way that at least one inter-metallic phase is formed between at least two metals of the group containing Ti, Al, Ni and V.

Abstract translation: 在一个实施方案中，在衬底上沉积第一Ti基层。 中间Al基层沉积在第一层上，第二NiV基层沉积在中间层上，第三Ag基层沉积在第二层上。 层叠体以这样一种方式进行回火，使得在至少两种含Ti，Al，Ni和V的金属之间形成至少一个金属间相。

公开(公告)号：US10115688B2

公开(公告)日：2018-10-30

申请号：US14726078

申请日：2015-05-29

Applicant: Infineon Technologies AG

Inventor： Kamil Karlovsky ,  Evelyn Napetschnig ,  Michael Ehmann ,  Mark Harrison ,  Anton Pugatschow

IPC: H01L21/44 ,  H01L23/00

Abstract: A semiconductor device includes a contact metal layer disposed over a semiconductor surface of a substrate, a diffusion barrier layer disposed over the contact metal layer, an inert layer disposed over the diffusion barrier layer, and a solder layer disposed over inert layer.

公开(公告)号：US20160351516A1

公开(公告)日：2016-12-01

申请号：US14726078

申请日：2015-05-29

Applicant: Infineon Technologies AG

Inventor： Kamil Karlovsky ,  Evelyn Napetschnig ,  Michael Ehmann ,  Mark Harrison ,  Anton Pugatschow

IPC: H01L23/00

CPC classification number: H01L24/05 ,  H01L24/03 ,  H01L24/83 ,  H01L2224/0401 ,  H01L2224/0558 ,  H01L2224/05599 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953

Abstract: A semiconductor device includes a contact metal layer disposed over a semiconductor surface of a substrate, a diffusion barrier layer disposed over the contact metal layer, an inert layer disposed over the diffusion barrier layer, and a solder layer disposed over inert layer.

Abstract translation: 半导体器件包括设置在衬底的半导体表面上的接触金属层，设置在接触金属层上的扩散阻挡层，设置在扩散阻挡层上的惰性层和设置在惰性层上的焊料层。

公开(公告)号：US20150228607A1

公开(公告)日：2015-08-13

申请号：US14692815

申请日：2015-04-22

Applicant: Infineon Technologies AG

Inventor： Tobias Schmidt ,  Evelyn Napetschnig ,  Franz Stueckler ,  Anton Pugatschow ,  Mark Harrison

IPC: H01L23/00

CPC classification number: H01L24/32 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/83 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/05082 ,  H01L2224/05083 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/0516 ,  H01L2224/05164 ,  H01L2224/05166 ,  H01L2224/0517 ,  H01L2224/05171 ,  H01L2224/05172 ,  H01L2224/05179 ,  H01L2224/0518 ,  H01L2224/05181 ,  H01L2224/05184 ,  H01L2224/05611 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/06181 ,  H01L2224/29082 ,  H01L2224/32227 ,  H01L2224/83805 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/0104 ,  H01L2924/01041 ,  H01L2924/01042 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01072 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/10335 ,  H01L2924/10337 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/00

Abstract: In various embodiments, a layer stack is provided. The layer stack may include a carrier; a first metal disposed over the carrier; a second metal disposed over the first metal; and a solder material disposed above the second metal or a material that provides contact to a solder that is supplied by an external source. The second metal may have a melting temperature of at least 1800° C. and is not or substantially not dissolved in the solder material at least one of during a soldering process and after the soldering process.

Abstract translation: 在各种实施例中，提供层叠。 层叠可以包括载体; 设置在载体上的第一金属; 设置在所述第一金属上的第二金属; 以及设置在第二金属上方的焊料材料或提供与由外部源供应的焊料的接触的材料。 第二金属可以具有至少1800℃的熔融温度，并且在焊接工艺期间和焊接工艺之后至少一个焊料材料中不会或基本上不溶解。

公开(公告)号：US08866299B2

公开(公告)日：2014-10-21

申请号：US13932851

申请日：2013-07-01

Applicant: Infineon Technologies AG

Inventor： Mark Harrison ,  Evelyn Napetschnig ,  Franz Stueckler

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/00 ,  H01L21/3065 ,  H01L21/02 ,  H01L21/683

CPC classification number: H01L21/3065 ,  H01L21/02057 ,  H01L21/6836 ,  H01L24/03 ,  H01L24/05 ,  H01L2221/68327 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/0401 ,  H01L2224/04026 ,  H01L2224/04042 ,  H01L2224/05005 ,  H01L2224/05083 ,  H01L2224/05099 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05172 ,  H01L2224/05184 ,  H01L2224/05541 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/94 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01072 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/10329 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/00014 ,  H01L2224/03 ,  H01L2924/047 ,  H01L2924/00

Abstract: A semiconductor device includes a workpiece having a bottom surface opposite the top surface. Metallization layers are disposed over the top surface and a protective layer is disposed over the metallization layers. The semiconductor device further includes a metal silicide layer disposed on the bottom surface. The metal silicide layer is less than about five atomic layers in thickness. A first metal layer is disposed over the metal silicide layer such that a metal of the first metal layer is the same as a metal of the metal silicide layer.

Abstract translation: 半导体器件包括具有与顶表面相对的底表面的工件。 金属化层设置在顶表面上方，并且保护层设置在金属化层上。 半导体器件还包括设置在底表面上的金属硅化物层。 金属硅化物层的厚度小于约5个原子层。 第一金属层设置在金属硅化物层上方，使得第一金属层的金属与金属硅化物层的金属相同。

公开(公告)号：US09006899B2

公开(公告)日：2015-04-14

申请号：US13716017

申请日：2012-12-14

Applicant: Infineon Technologies AG

Inventor： Paul Ganitzer ,  Kurt Matoy ,  Martin Sporn ,  Mark Harrison

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/498 ,  H01L21/02

CPC classification number: H01L23/49866 ,  H01L21/02697 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L24/29 ,  H01L2224/0347 ,  H01L2224/03848 ,  H01L2224/0401 ,  H01L2224/04026 ,  H01L2224/05083 ,  H01L2224/05124 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05172 ,  H01L2224/05639 ,  H01L2224/13111 ,  H01L2224/29111 ,  H01L2924/0002 ,  H01L2924/10253 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/01023

Abstract: In one embodiment method, a first Ti based layer is deposited on the substrate. An intermediate Al based layer is deposited on the first layer, a second NiV based layer is deposited on the intermediate layer, and a third Ag based layer is deposited on the second layer. The layer stack is tempered in such a way that at least one inter-metallic phase is formed between at least two metals of the group containing Ti, Al, Ni and V.

Abstract translation: 在一个实施方案中，在衬底上沉积第一Ti基层。 中间Al基层沉积在第一层上，第二NiV基层沉积在中间层上，第三Ag基层沉积在第二层上。 层叠体以这样一种方式进行回火，使得在至少两种含Ti，Al，Ni和V的金属之间形成至少一个金属间相。