公开(公告)号：US20210183763A1

公开(公告)日：2021-06-17

申请号：US17170359

申请日：2021-02-08

Applicant: Infineon Technologies AG

Inventor： Paul Ganitzer ,  Martin Poelzl

IPC: H01L23/528 ,  H01L23/532 ,  H01L23/535 ,  H01L21/78 ,  H01L23/495 ,  H01L21/48 ,  H01L29/78 ,  H01L23/482 ,  H01L21/683 ,  H01L21/3213

Abstract: A semiconductor device includes a semiconductor layer with a thickness of at most 50 μm. A first metallization structure is disposed on a first surface of the semiconductor layer. The first metallization structure includes a first copper region with a first thickness. A second metallization structure is disposed on a second surface of the semiconductor layer opposite to the first surface. The second metallization structure includes a second copper region with a second thickness.

公开(公告)号：US10971449B2

公开(公告)日：2021-04-06

申请号：US16722734

申请日：2019-12-20

Applicant: Infineon Technologies AG

Inventor： Paul Ganitzer ,  Martin Poelzl

IPC: H01L23/528 ,  H01L23/532 ,  H01L23/535 ,  H01L21/78 ,  H01L23/495 ,  H01L21/48 ,  H01L29/78 ,  H01L23/482 ,  H01L21/683 ,  H01L21/3213 ,  H01L23/31 ,  H01L29/40 ,  H01L23/00

Abstract: A semiconductor device includes a semiconductor layer with a thickness of at most 50 μm. A first metallization structure is disposed on a first surface of the semiconductor layer. The first metallization structure includes a first copper region with a first thickness. A second metallization structure is disposed on a second surface of the semiconductor layer opposite to the first surface. The second metallization structure includes a second copper region with a second thickness. The total thickness, which is the sum of the first thickness and the second thickness, deviates from the thickness of the semiconductor layer by not more than 20% and a difference between the first thickness and the second thickness is not more than 20% of the total thickness.

公开(公告)号：US10593623B2

公开(公告)日：2020-03-17

申请号：US15804396

申请日：2017-11-06

Applicant: Infineon Technologies AG

Inventor： Paul Ganitzer ,  Martin Poelzl

IPC: H01L23/528 ,  H01L23/532 ,  H01L23/535 ,  H01L21/78 ,  H01L23/495 ,  H01L21/48 ,  H01L29/78 ,  H01L23/482 ,  H01L21/683 ,  H01L21/3213 ,  H01L23/00 ,  H01L23/31 ,  H01L29/40

Abstract: A semiconductor device includes a semiconductor layer with a thickness of at most 50 μm. A first metallization structure is disposed on a first surface of the semiconductor layer. The first metallization structure includes a first copper region with a first thickness. A second metallization structure is disposed on a second surface of the semiconductor layer opposite to the first surface. The second metallization structure includes a second copper region with a second thickness. The total thickness, which is the sum of the first thickness and the second thickness, deviates from the thickness of the semiconductor layer by not more than 20% and a difference between the first thickness and the second thickness is not more than 20% of the total thickness.

公开(公告)号：US09397055B2

公开(公告)日：2016-07-19

申请号：US14290448

申请日：2014-05-29

Applicant: Infineon Technologies AG

Inventor： Paul Ganitzer ,  Rudolf Zelsacher

IPC: H01L21/00 ,  H01L23/00 ,  H01L21/82

CPC classification number: H01L24/03 ,  H01L21/6835 ,  H01L21/6836 ,  H01L21/82 ,  H01L24/05 ,  H01L2221/68327 ,  H01L2221/68336 ,  H01L2221/6834 ,  H01L2224/03002 ,  H01L2224/0312 ,  H01L2224/0345 ,  H01L2224/03464 ,  H01L2224/0347 ,  H01L2224/0348 ,  H01L2224/0361 ,  H01L2224/03614 ,  H01L2224/0362 ,  H01L2224/05016 ,  H01L2224/05022 ,  H01L2224/05023 ,  H01L2224/05082 ,  H01L2224/05084 ,  H01L2224/05111 ,  H01L2224/05124 ,  H01L2224/05562 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/05582 ,  H01L2224/05583 ,  H01L2224/05611 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05664 ,  H01L2224/05672 ,  H01L2224/80203 ,  H01L2224/80825 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01042 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/0132 ,  H01L2224/03 ,  H01L2924/00014 ,  H01L2224/05624

Abstract: In an embodiment of the present invention, a method of forming a semiconductor device includes providing a semiconductor substrate including a first chip region and a second chip region. A first contact pad is formed over the first chip region and a second contact pad is formed over the second chip region. The first and the second contact pads are at least as thick as the semiconductor substrate. The method further includes dicing through the semiconductor substrate between the first and the second contact pads. The dicing is performed from a side of the semiconductor substrate including the first contact pad and the second contact pad. A conductive liner is formed over the first and the second contact pads and sidewalls of the semiconductor substrate exposed by the dicing.

Abstract translation: 在本发明的实施例中，形成半导体器件的方法包括提供包括第一芯片区域和第二芯片区域的半导体衬底。 在第一芯片区域上形成第一接触焊盘，并且在第二芯片区域上形成第二接触焊盘。 第一和第二接触焊盘至少与半导体衬底一样厚。 该方法还包括在第一和第二接触焊盘之间切割通过半导体衬底。 从包括第一接触焊盘和第二接触焊盘的半导体衬底的一侧进行切割。 导电衬垫形成在半导体衬底的第一接触焊盘和第二接触焊盘和通过切割而暴露的侧壁之间。

公开(公告)号：US11302579B2

公开(公告)日：2022-04-12

申请号：US16874146

申请日：2020-05-14

Applicant: Infineon Technologies AG

Inventor： Paul Ganitzer ,  Carsten von Koblinski ,  Thomas Feil ,  Gerald Lackner ,  Jochen Mueller ,  Martin Poelzl ,  Tobias Polster

IPC: H01L23/48 ,  H01L21/8234 ,  H01L21/56 ,  H01L21/78 ,  H01L23/495 ,  H01L21/762 ,  H01L21/768 ,  H01L25/065 ,  H01L23/31

Abstract: In an embodiment, a composite semiconductor substrate includes a first polymer layer and a plurality of semiconductor dies having a first surface, a second surface opposing the first surface, side faces extending between the first surface and the second surface and a first metallization structure on the first surface. Edge regions of the first surface and at least portions of the side faces are embedded in the first polymer layer. At least one metallic region of the first metallization structure is exposed from the first polymer layer. A second metallization structure is arranged on the second surface of the plurality of semiconductor dies. A second polymer layer is arranged on edge regions of the second surface of the plurality of semiconductor dies and on the first polymer layer in regions between the side faces of neighbouring ones of the plurality of semiconductor dies.

公开(公告)号：US20140167270A1

公开(公告)日：2014-06-19

申请号：US13716017

申请日：2012-12-14

Applicant: INFINEON TECHNOLOGIES AG

Inventor： Paul Ganitzer ,  Kurt Matoy ,  Martin Sporn ,  Mark Harrison

IPC: H01L23/498 ,  H01L21/02

CPC classification number: H01L23/49866 ,  H01L21/02697 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L24/29 ,  H01L2224/0347 ,  H01L2224/03848 ,  H01L2224/0401 ,  H01L2224/04026 ,  H01L2224/05083 ,  H01L2224/05124 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05172 ,  H01L2224/05639 ,  H01L2224/13111 ,  H01L2224/29111 ,  H01L2924/0002 ,  H01L2924/10253 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/01023

Abstract: In one embodiment method, a first Ti based layer is deposited on the substrate. An intermediate Al based layer is deposited on the first layer, a second NiV based layer is deposited on the intermediate layer, and a third Ag based layer is deposited on the second layer. The layer stack is tempered in such a way that at least one inter-metallic phase is formed between at least two metals of the group containing Ti, Al, Ni and V.

Abstract translation: 在一个实施方案中，在衬底上沉积第一Ti基层。 中间Al基层沉积在第一层上，第二NiV基层沉积在中间层上，第三Ag基层沉积在第二层上。 层叠体以这样一种方式进行回火，使得在至少两种含Ti，Al，Ni和V的金属之间形成至少一个金属间相。

公开(公告)号：US20200273750A1

公开(公告)日：2020-08-27

申请号：US16874146

申请日：2020-05-14

Applicant: Infineon Technologies AG

Inventor： Paul Ganitzer ,  Carsten von Koblinski ,  Thomas Feil ,  Gerald Lackner ,  Jochen Mueller ,  Martin Poelzl ,  Tobias Polster

IPC: H01L21/8234 ,  H01L21/56 ,  H01L21/78 ,  H01L23/495 ,  H01L21/762 ,  H01L21/768 ,  H01L23/48 ,  H01L25/065

Abstract: In an embodiment, a composite semiconductor substrate includes a first polymer layer and a plurality of semiconductor dies having a first surface, a second surface opposing the first surface, side faces extending between the first surface and the second surface and a first metallization structure on the first surface. Edge regions of the first surface and at least portions of the side faces are embedded in the first polymer layer. At least one metallic region of the first metallization structure is exposed from the first polymer layer. A second metallization structure is arranged on the second surface of the plurality of semiconductor dies. A second polymer layer is arranged on edge regions of the second surface of the plurality of semiconductor dies and on the first polymer layer in regions between the side faces of neighbouring ones of the plurality of semiconductor dies.

公开(公告)号：US10573533B2

公开(公告)日：2020-02-25

申请号：US16116210

申请日：2018-08-29

Applicant: Infineon Technologies AG

Inventor： Edward Fuergut ,  Irmgard Escher-Poeppel ,  Stephanie Fassl ,  Paul Ganitzer ,  Gerhard Poeppel ,  Werner Schustereder ,  Harald Wiedenhofer

IPC: H01L21/324 ,  H01L23/31 ,  H01L21/268 ,  H01L21/04 ,  H01L21/225 ,  H01L21/285

Abstract: Various embodiments provide a method of reducing a sheet resistance in an electronic device encapsulated at least partially in an encapsulation material, wherein the method comprises: providing an electronic device comprising a multilayer structure and being at least partially encapsulated by an encapsulation material; and locally introducing energy into the multilayer structure for reducing a sheet resistance.

公开(公告)号：US20190013210A1

公开(公告)日：2019-01-10

申请号：US16116210

申请日：2018-08-29

Applicant: Infineon Technologies AG

Inventor： Edward Fuergut ,  Irmgard Escher-Poeppel ,  Stephanie Fassl ,  Paul Ganitzer ,  Gerhard Poeppel ,  Werner Schustereder ,  Harald Wiedenhofer

IPC: H01L21/324 ,  H01L21/285 ,  H01L21/225 ,  H01L21/04 ,  H01L21/321 ,  H01L21/268 ,  H01L23/31

CPC classification number: H01L21/324 ,  H01L21/0455 ,  H01L21/0485 ,  H01L21/2254 ,  H01L21/2258 ,  H01L21/268 ,  H01L21/28512 ,  H01L21/28575 ,  H01L23/3157

Abstract: Various embodiments provide a method of reducing a sheet resistance in an electronic device encapsulated at least partially in an encapsulation material, wherein the method comprises: providing an electronic device comprising a multilayer structure and being at least partially encapsulated by an encapsulation material; and locally introducing energy into the multilayer structure for reducing a sheet resistance.

公开(公告)号：US09673157B2

公开(公告)日：2017-06-06

申请号：US15195434

申请日：2016-06-28

Applicant: Infineon Technologies AG

Inventor： Paul Ganitzer ,  Rudolf Zelsacher

IPC: H01L21/00 ,  H01L23/00 ,  H01L21/82 ,  H01L21/683

CPC classification number: H01L24/03 ,  H01L21/6835 ,  H01L21/6836 ,  H01L21/82 ,  H01L24/05 ,  H01L2221/68327 ,  H01L2221/68336 ,  H01L2221/6834 ,  H01L2224/03002 ,  H01L2224/0312 ,  H01L2224/0345 ,  H01L2224/03464 ,  H01L2224/0347 ,  H01L2224/0348 ,  H01L2224/0361 ,  H01L2224/03614 ,  H01L2224/0362 ,  H01L2224/05016 ,  H01L2224/05022 ,  H01L2224/05023 ,  H01L2224/05082 ,  H01L2224/05084 ,  H01L2224/05111 ,  H01L2224/05124 ,  H01L2224/05562 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/05582 ,  H01L2224/05583 ,  H01L2224/05611 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05664 ,  H01L2224/05672 ,  H01L2224/80203 ,  H01L2224/80825 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01042 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/0132 ,  H01L2224/03 ,  H01L2924/00014 ,  H01L2224/05624

Abstract: In an embodiment of the present invention, a method of forming a semiconductor device includes providing a semiconductor substrate including a first chip region and a second chip region. A first contact pad is formed over the first chip region and a second contact pad is formed over the second chip region. The first and the second contact pads are at least as thick as the semiconductor substrate. The method further includes dicing through the semiconductor substrate between the first and the second contact pads. The dicing is performed from a side of the semiconductor substrate including the first contact pad and the second contact pad. A conductive liner is formed over the first and the second contact pads and sidewalls of the semiconductor substrate exposed by the dicing.