公开(公告)号：US20170092573A1

公开(公告)日：2017-03-30

申请号：US14866491

申请日：2015-09-25

Applicant: INTEL CORPORATION

Inventor： Mathew J. MANUSHAROW ,  Daniel N. SOBIESKI ,  Mihir K. ROY ,  William J. LAMBERT

IPC: H01L23/498 ,  H01L21/02 ,  H01L21/285 ,  H01L21/768 ,  H01L21/3205 ,  H01L23/00 ,  H01L21/32

CPC classification number: H01L23/49838 ,  H01L21/02263 ,  H01L21/28556 ,  H01L21/32 ,  H01L21/3205 ,  H01L21/4857 ,  H01L21/768 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/49894 ,  H01L24/11 ,  H01L24/16 ,  H01L2224/16227 ,  H01L2924/1205 ,  H05K1/162

Abstract: A hybrid pitch package includes a standard package pitch zone of the package having only standard package pitch sized features that is adjacent to a smaller processor pitch sized zone of the package having smaller processor pitch sized features. The package may be formed by obtaining a package having standard package pitch sized features (such as from another location or a package processing facility), forming a protective mask over a standard package pitch zone of the package that is adjacent to a smaller processor pitch sized zone on the package, and then forming smaller processor pitch sized features (such as contacts, traces and interconnects) in the smaller processor pitch sized zone at a chip fabrication processing facility. The smaller processor pitch sized features can be directly connected to (thus reducing the package connection area needed) a chip or device having processor pitch sized features (e.g., exposed contacts).

公开(公告)号：US20220230972A1

公开(公告)日：2022-07-21

申请号：US17714944

申请日：2022-04-06

Applicant: Intel Corporation

Inventor： Digvijay A. RAORANE ,  Ian En Yoon CHIN ,  Daniel N. SOBIESKI

IPC: H01L23/00 ,  H01L21/50 ,  H01L23/498

Abstract: Embodiments include semiconductor device packages and methods of forming such packages. In an embodiment, the package may include a die-side reinforcement layer with a cavity formed through the die-side reinforcement layer. A die having a first side and an opposite second side comprising a device side may be positioned in the cavity with the first side of the die being substantially coplanar with a first side of the die-side reinforcement layer. In an embodiment, a build-up structure may be coupled to a second side of the die. Embodiments include a build-up structure that includes a plurality of alternating layers of patterned conductive material and insulating material.

公开(公告)号：US20160329153A1

公开(公告)日：2016-11-10

申请号：US15214390

申请日：2016-07-19

Applicant: Intel Corporation

Inventor： Robert L. Sankman ,  Daniel N. SOBIESKI ,  Sri Ranga Sai BOYAPATI

IPC: H01G4/33 ,  H01L21/48 ,  H05K1/18 ,  H01L23/498

CPC classification number: H01G4/33 ,  H01L21/4857 ,  H01L23/49822 ,  H01L23/49827 ,  H01L2224/16225 ,  H01L2924/15311 ,  H05K1/09 ,  H05K1/115 ,  H05K1/162 ,  H05K1/185 ,  H05K3/0017 ,  H05K3/188 ,  H05K3/4644 ,  H05K3/467 ,  H05K2201/10015

Abstract: An embedded thin film capacitor and methods of its fabrication are disclosed. The embedded thin film capacitor includes two conductive plates separated by a dielectric layer. In embodiments, the capacitor is enclosed within a package substrate. A method of forming the embedded thin film capacitor includes forming a first insulating layer on a bottom plate and a first trace. A first opening is then formed in a first insulating layer to expose a first region of a bottom plate. An adhesive layer is then formed on the first insulating layer and on top of the exposed first region of the bottom plate. A second opening is formed through the insulating layer and the first insulating layer to expose a second region of the bottom plate. A top plate is formed within the first opening and a via is formed within the second opening.

公开(公告)号：US20200251426A1

公开(公告)日：2020-08-06

申请号：US16849707

申请日：2020-04-15

Applicant: Intel Corporation

Inventor： Digvijay A. RAORANE ,  Ian En Yoon CHIN ,  Daniel N. SOBIESKI

IPC: H01L23/00 ,  H01L23/498 ,  H01L21/50

Abstract: Embodiments include semiconductor device packages and methods of forming such packages. In an embodiment, the package may include a die-side reinforcement layer with a cavity formed through the die-side reinforcement layer. A die having a first side and an opposite second side comprising a device side may be positioned in the cavity with the first side of the die being substantially coplanar with a first side of the die-side reinforcement layer. In an embodiment, a build-up structure may be coupled to a second side of the die. Embodiments include a build-up structure that includes a plurality of alternating layers of patterned conductive material and insulating material.

公开(公告)号：US20180301423A1

公开(公告)日：2018-10-18

申请号：US15948958

申请日：2018-04-09

Applicant: Intel Corporation

Inventor： Digvijay A. RORANE ,  Ian En Yoon CHIN ,  Daniel N. SOBIESKI

IPC: H01L23/00 ,  H01L21/50 ,  H01L23/498

Abstract: Embodiments include semiconductor device packages and methods of forming such packages. In an embodiment, the package may include a die-side reinforcement layer with a cavity formed through the die-side reinforcement layer. A die having a first side and an opposite second side comprising a device side may be positioned in the cavity with the first side of the die being substantially coplanar with a first side of the die-side reinforcement layer. In an embodiment, a build-up structure may be coupled to a second side of the die. Embodiments include a build-up structure that includes a plurality of alternating layers of patterned conductive material and insulating material.

公开(公告)号：US20160088738A1

公开(公告)日：2016-03-24

申请号：US14956214

申请日：2015-12-01

Applicant: Intel Corporation

Inventor： Digvijay A. RAORANE ,  Kemal AYGUN ,  Daniel N. SOBIESKI ,  Drew W. DELANEY

IPC: H05K3/00 ,  H05K3/02 ,  H05K1/02 ,  H05K3/30

CPC classification number: H05K3/007 ,  C23C14/14 ,  H01L21/4857 ,  H01L21/561 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/49822 ,  H01L23/5389 ,  H01L23/552 ,  H01L24/19 ,  H01L24/97 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16227 ,  H01L2224/19 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2224/97 ,  H01L2924/1815 ,  H01L2924/18162 ,  H05K1/0219 ,  H05K1/185 ,  H05K3/02 ,  H05K3/30 ,  H05K3/4682 ,  H05K2201/0715 ,  H05K2203/1469 ,  H05K2203/308 ,  H01L2224/83 ,  H01L2224/82 ,  H01L2224/83005

Abstract: An apparatus including a die including a device side with contact points and lateral sidewalls defining a thickness of the die; a build-up carrier coupled to the die, the build-up carrier including a plurality of alternating layers of patterned conductive material and insulating material, wherein at least one of the layers of patterned conductive material is coupled to one of the contact points of the die; and an interference shield including a conductive material disposed on the die and a portion of the build-up carrier. The apparatus may be connected to a printed circuit board. A method including forming a build-up carrier adjacent a device side of a die including a plurality of alternating layers of patterned conductive material and insulating material; and forming a interference shield on a portion of the build-up carrier.