公开(公告)号：US20180329240A1

公开(公告)日：2018-11-15

申请号：US15774432

申请日：2015-12-26

Applicant: Intel Corporation

Inventor： Vivek RAGHUNATHAN ,  Mihir K. ROY ,  Ravindranath V. MAHAJAN

IPC: G02F1/13357 ,  H05K1/18 ,  H05K1/02 ,  H05K3/30 ,  H01S3/04

CPC classification number: G02F1/1336 ,  G02F2001/133628 ,  G06F1/20 ,  H01S3/0408 ,  H04B1/38 ,  H04B1/385 ,  H05K1/0203 ,  H05K1/181 ,  H05K3/303 ,  H05K2201/10121 ,  H05K2201/10522

Abstract: Embodiments are generally directed to a self-cooled laser integrated device and substrate architecture. An embodiment of a device includes a substrate or printed circuit board (PCB); a component coupled with the substrate or PCB, the component including an cooling agent on at least one side of the component; one or more laser sources, at least a first laser source of the one or more laser sources being implemented to direct laser light onto the cooling agent; and a controller to drive the laser source, wherein the cooling agent provides cooling for the component when the laser light is directed on the engineered cooling agent.

公开(公告)号：US20180331003A1

公开(公告)日：2018-11-15

申请号：US15776755

申请日：2015-12-16

Applicant: Intel Corporation

Inventor： Krishna BHARATH ,  Mathew J. MANUSHAROW ,  Adel A. ELSHERBINI ,  Mihir K. ROY ,  Aleksandar ALEKSOV ,  Yidnekachew S. MEKONNEN ,  Javier SOTO GONZALEZ ,  Feras EID ,  Suddhasattwa NAD ,  Meizi JIAO

IPC: H01L23/12 ,  H01L21/48 ,  H01L23/498

CPC classification number: H01L23/12 ,  H01L21/486 ,  H01L23/48 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838

Abstract: Embodiments of the invention include an electrical package and methods of forming the package. In one embodiment, the electrical package may include a first package layer. A plurality of signal lines with a first thickness may be formed on the first package layer. Additionally, a power plane with a second thickness may be formed on the first package layer. According to an embodiment, the second thickness is greater than the first thickness. Embodiments of the invention may form the power plane with a lithographic patterning and deposition process that is different than the lithographic patterning and deposition process used to form the plurality of signal lines. In an embodiment, the power plane may be formed concurrently with vias that electrically couple the signal lines to the next routing layer.

公开(公告)号：US20180332708A1

公开(公告)日：2018-11-15

申请号：US15774263

申请日：2015-12-26

Applicant: Intel Corporation

Inventor： William J. LAMBERT ,  Mihir K. ROY ,  Mathew J. MANUSHAROW

IPC: H05K1/18 ,  H01L25/16 ,  H01L23/498 ,  H01L21/48 ,  H05K3/00 ,  H05K3/40

CPC classification number: H05K1/185 ,  H01L21/486 ,  H01L23/49827 ,  H01L25/16 ,  H05K1/181 ,  H05K3/0047 ,  H05K3/3436 ,  H05K3/4038 ,  H05K2201/10015 ,  H05K2201/1003 ,  H05K2201/10454 ,  H05K2201/10515 ,  H05K2201/10651

Abstract: Embodiments are generally directed to vertically embedded passive components. An embodiment of a device includes a semiconductor die; and a package coupled with the semiconductor die. The package includes one or more passive components connected with the semiconductor die, the one or more passive components being embedded vertically in the package substrate, each of the passive components including a first terminal and a second terminal. A first passive component is embedded in a through hole drilled in the package, the first terminal of the first passive component being connected to the semiconductor die by a via through an upper buildup layer on the package.

公开(公告)号：US20170092573A1

公开(公告)日：2017-03-30

申请号：US14866491

申请日：2015-09-25

Applicant: INTEL CORPORATION

Inventor： Mathew J. MANUSHAROW ,  Daniel N. SOBIESKI ,  Mihir K. ROY ,  William J. LAMBERT

IPC: H01L23/498 ,  H01L21/02 ,  H01L21/285 ,  H01L21/768 ,  H01L21/3205 ,  H01L23/00 ,  H01L21/32

CPC classification number: H01L23/49838 ,  H01L21/02263 ,  H01L21/28556 ,  H01L21/32 ,  H01L21/3205 ,  H01L21/4857 ,  H01L21/768 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/49894 ,  H01L24/11 ,  H01L24/16 ,  H01L2224/16227 ,  H01L2924/1205 ,  H05K1/162

Abstract: A hybrid pitch package includes a standard package pitch zone of the package having only standard package pitch sized features that is adjacent to a smaller processor pitch sized zone of the package having smaller processor pitch sized features. The package may be formed by obtaining a package having standard package pitch sized features (such as from another location or a package processing facility), forming a protective mask over a standard package pitch zone of the package that is adjacent to a smaller processor pitch sized zone on the package, and then forming smaller processor pitch sized features (such as contacts, traces and interconnects) in the smaller processor pitch sized zone at a chip fabrication processing facility. The smaller processor pitch sized features can be directly connected to (thus reducing the package connection area needed) a chip or device having processor pitch sized features (e.g., exposed contacts).

公开(公告)号：US20150318238A1

公开(公告)日：2015-11-05

申请号：US14798395

申请日：2015-07-13

Applicant: Intel Corporation

Inventor： Mark S. HLAD ,  Islam A. SALAMA ,  Mihir K. ROY ,  Tao WU ,  Yueli LIU ,  Kyu Oh LEE

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/50 ,  H01L21/48

CPC classification number: H01L23/49838 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/563 ,  H01L23/49811 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49866 ,  H01L23/50 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L2224/1112 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/11466 ,  H01L2224/119 ,  H01L2224/13005 ,  H01L2224/13082 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/1601 ,  H01L2224/16225 ,  H01L2224/16238 ,  H01L2224/165 ,  H01L2224/2919 ,  H01L2224/73204 ,  H01L2224/81121 ,  H01L2224/81191 ,  H01L2224/81444 ,  H01L2224/81455 ,  H01L2224/81464 ,  H01L2224/81815 ,  H01L2224/831 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01046 ,  H01L2924/01079 ,  H01L2924/01103 ,  H01L2924/01108 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15321 ,  H01L2924/2064 ,  H01L2924/37001 ,  H01L2924/3841 ,  H05K1/113 ,  H05K3/107 ,  H05K3/3436 ,  H05K3/421 ,  H01L2924/00014 ,  H01L2924/00

Abstract: Package substrates enabling reduced bump pitches and package assemblies thereof. Surface-level metal features are embedded in a surface-level dielectric layer with surface finish protruding from a top surface of the surface-level dielectric for assembly, without solder resist, to an IC chip having soldered connection points. Package substrates are fabricated to enable multiple levels of trace routing with each trace routing level capable of reduced minimum trace width and spacing.

Abstract translation: 封装衬底，能够减少凸起间距和封装组件。 表面级金属特征嵌入表面级电介质层中，其表面光洁度从表面电介质的顶表面突出，用于组装而无阻焊，具有焊接连接点的IC芯片。 制造封装衬底以实现多级跟踪路由，每个跟踪路由级别能够减少最小迹线宽度和间距。