公开(公告)号：US20250006630A1

公开(公告)日：2025-01-02

申请号：US18342130

申请日：2023-06-27

Applicant: Intel Corporation

Inventor： Carla Moran Guizan ,  Peter Baumgartner ,  Thomas Wagner ,  Georg Seidemann ,  Michael Langenbuch ,  Mamatha Yakkegondi Virupakshappa ,  Jonathan Jensen ,  Roshini Sachithanandan ,  Philipp Riess

IPC: H01L23/522 ,  H01L23/00 ,  H01L23/528 ,  H01L25/065

Abstract: Described herein are integrated circuit devices that include conductive structures formed by direct bonding of different components, e.g., direct bonding of two dies, or of a die to a wafer. The conductive structures are formed from a top metallization layer of each of the components. For example, elongated conductive structures at the top metallization layer may be patterned and bonded to form large interconnects for high-frequency and/or high-power signals. In another example, the bonded conductive structures may form radio frequency passive devices, such as inductors or transformers.

公开(公告)号：US20240364002A1

公开(公告)日：2024-10-31

申请号：US18139206

申请日：2023-04-25

Applicant: Intel Corporation

Inventor： Harald Gossner ,  Thomas Wagner ,  Bernd Waidhas ,  Georg Seidemann ,  Tae Young Yang ,  Telesphor Kamgaing

IPC: H01Q1/50 ,  H01Q1/22 ,  H01Q9/04

CPC classification number: H01Q1/50 ,  H01Q1/2283 ,  H01Q9/045

Abstract: An antenna device includes integrated polymer nanocomposite (PNC) devices coupling an antenna on a substrate to both ground and signal terminals. The PNC devices may include PNC material between two electrodes. The PNC devices may be integrated into the antenna device with the substrate including at least one electrode of each of the PNC devices. One PNC device may convey a signal to or from the antenna, e.g., between the antenna and a signal terminal. Another PNC device may convey an electrostatic discharge (ESD) pulse to a ground terminal. The antenna device may include or be coupled to an integrated circuit (IC) die. The IC die may couple to the signal and ground terminals, e.g., opposite the substrate from the antenna.

公开(公告)号：US12080655B2

公开(公告)日：2024-09-03

申请号：US16368032

申请日：2019-03-28

Applicant: Intel Corporation

Inventor： Gianni Signorini ,  Georg Seidemann ,  Bernd Waidhas

IPC: H01L23/552 ,  H01L21/48 ,  H01L21/78 ,  H01L23/31 ,  H01L23/498

CPC classification number: H01L23/552 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/78 ,  H01L23/3114 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49838

Abstract: Embodiments disclosed herein include electronic packages with conformal shields and methods of forming such packages. In an embodiment, the electronic package comprises a die having a first surface, a second surface opposite the first surface, and sidewall surfaces. A redistribution layer is over the first surface of the die, and the redistribution layer comprises a first conductive layer. In an embodiment, an under ball metallization (UBM) layer is over the redistribution layer, and a conductive shield is over the sidewall surfaces of the die and the second surface of the die. In an embodiment, the conductive shield is electrically coupled to the UBM layer.

公开(公告)号：US20220415814A1

公开(公告)日：2022-12-29

申请号：US17355763

申请日：2021-06-23

Applicant: Intel Corporation

Inventor： Bernd Waidhas ,  Carlton Hanna ,  Stephen Morein ,  Lizabeth Keser ,  Georg Seidemann

IPC: H01L23/538 ,  H01L25/16 ,  H05K1/18 ,  H01L25/065 ,  H01L25/18 ,  H01L23/00 ,  H01L23/367 ,  H01L25/00 ,  H01L23/48

Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a package substrate including a first conductive pathway electrically coupled to a power source; a first microelectronic component embedded in an insulating material on the surface of the package substrate and including a TSV electrically coupled to the first conductive pathway; a redistribution layer (RDL) on the insulating material including a second conductive pathway electrically coupled to the TSV; and a second microelectronic component on the RDL and electrically coupled to the second conductive pathway, wherein the second conductive pathway electrically couples the TSV, the second microelectronic component, and the first microelectronic component.

公开(公告)号：US11469213B2

公开(公告)日：2022-10-11

申请号：US16325970

申请日：2016-09-28

Applicant: Intel Corporation

Inventor： Georg Seidemann ,  Thomas Wagner ,  Klaus Reingruber ,  Bernd Waidhas ,  Andreas Wolter

IPC: H01L25/065 ,  H01L23/498 ,  H01L23/00 ,  H01L29/06 ,  H01L23/31

Abstract: In accordance with disclosed embodiments, there are provided methods, systems, and apparatuses for implementing reduced height semiconductor packages for mobile electronics. For instance, there is disclosed in accordance with one embodiment a stacked die package having therein a bottom functional silicon die; a recess formed within the bottom functional silicon die by a thinning etch partially reducing a vertical height of the bottom functional silicon die at the recess; and a top component positioned at least partially within the recess formed within the bottom functional silicon die. Other related embodiments are disclosed.

公开(公告)号：US11424209B2

公开(公告)日：2022-08-23

申请号：US16871325

申请日：2020-05-11

Applicant: Intel Corporation

Inventor： Sven Albers ,  Klaus Reingruber ,  Georg Seidemann ,  Christian Geissler ,  Richard Patten

IPC: H01L23/552 ,  H01L23/00 ,  H01L23/433 ,  H01L21/56 ,  H01L21/48 ,  H01L23/31 ,  H01L23/36 ,  H01L23/498

Abstract: An apparatus is described that includes a redistribution layer and a semiconductor die on the redistribution layer. An electrically conductive layer resides over the semiconductor die. A compound mold resides over the electrically conductive layer.

公开(公告)号：US11374323B2

公开(公告)日：2022-06-28

申请号：US16473566

申请日：2017-03-31

Applicant: Intel Corporation

Inventor： Andreas Augustin ,  Sonja Koller ,  Bernd Waidhas ,  Georg Seidemann ,  Andreas Wolter ,  Stephan Stoeckl ,  Thomas Wagner ,  Josef Hagn

IPC: H01Q9/04 ,  H01L23/00 ,  H01Q1/22 ,  H01Q21/06

Abstract: A patch antenna array is fabricated with a package-on-package setup that contains a transceiver. The patch antenna array has a footprint that intersects the transceiver footprint. The package-on-package setup includes through-mold vias that couple to a redistribution layer disposed between the patch antennas and the package-on-package setup.

公开(公告)号：US11081541B2

公开(公告)日：2021-08-03

申请号：US16881954

申请日：2020-05-22

Applicant: Intel Corporation

Inventor： Veronica Sciriha ,  Georg Seidemann

IPC: H01L23/64 ,  H01L49/02 ,  H01L23/522 ,  H01L23/00

Abstract: A system and method of providing a coil in an electronic communication device in is disclosed. Multiple dielectric layers are deposited and patterned on a semiconductor substrate or insulating mold compound. The dielectric layers provide conductive contact with a contact pad on the underlying structure. Shielding for the coil, including a seed layer covered by an insulating material, is disposed in a via of a lowermost of the dielectric layers. Grounding of the shielding seed layer is through a contact pad on the substrate or a trace between the dielectric layers. A coil is fabricated over the shielding and a solder mask deposited and patterned to cover and insulate the coil. The coil is fabricated in a via of a dielectric layer immediately below the solder mask or above this dielectric layer. Electrical contact is provided by multiple copper and seed layers in the solder mask and dielectric layers.

公开(公告)号：US10403602B2

公开(公告)日：2019-09-03

申请号：US15637935

申请日：2017-06-29

Applicant: Intel Corporation

Inventor： Bernd Waidhas ,  Georg Seidemann ,  Andreas Augustin ,  Laurent Millou ,  Andreas Wolter ,  Reinhard Mahnkopf ,  Stephan Stoeckl ,  Thomas Wagner

IPC: H01L21/48 ,  H01L25/065 ,  H01L23/48 ,  G06F15/76 ,  H01L25/00

Abstract: A semiconductive device stack, includes a baseband processor die with an active surface and a backside surface, and a recess in the backside surface. A recess-seated device is disposed in the recess, and a through-silicon via in the baseband processor die couples the baseband processor die at the active surface to the recess-seated die at the recess. A processor die is disposed on the baseband processor die backside surface, and a memory die is disposed on the processor die. The several dice are coupled by through-silicon via groups.

公开(公告)号：US09997444B2

公开(公告)日：2018-06-12

申请号：US15117716

申请日：2014-03-12

Applicant: INTEL CORPORATION

Inventor： Thorsten Meyer ,  Gerald Ofner ,  Andreas Wolter ,  Georg Seidemann ,  Sven Albers ,  Christian Geissler

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L21/48 ,  H01L21/56 ,  H01L23/50 ,  H01L25/16 ,  H01L23/13

CPC classification number: H01L23/49838 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/565 ,  H01L23/13 ,  H01L23/3114 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/50 ,  H01L24/16 ,  H01L24/19 ,  H01L24/20 ,  H01L24/96 ,  H01L25/16 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16227 ,  H01L2224/24195 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2924/15151 ,  H01L2924/15159 ,  H01L2924/15174 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/1815 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105

Abstract: A microelectronic package including a passive microelectronic device disposed within a package body, wherein the package body is the portion of the microelectronic package which provides support and/or rigidity to the microelectronic package. In a flip-chip type microelectronic package, the package body may comprise a microelectronic substrate to which an active microelectronic device is electrically attached. In an embedded device type microelectronic package, the package body may comprise the material in which the active microelectronic device is embedded.