公开(公告)号：US11424209B2

公开(公告)日：2022-08-23

申请号：US16871325

申请日：2020-05-11

Applicant: Intel Corporation

Inventor： Sven Albers ,  Klaus Reingruber ,  Georg Seidemann ,  Christian Geissler ,  Richard Patten

IPC: H01L23/552 ,  H01L23/00 ,  H01L23/433 ,  H01L21/56 ,  H01L21/48 ,  H01L23/31 ,  H01L23/36 ,  H01L23/498

Abstract: An apparatus is described that includes a redistribution layer and a semiconductor die on the redistribution layer. An electrically conductive layer resides over the semiconductor die. A compound mold resides over the electrically conductive layer.

公开(公告)号：US09997444B2

公开(公告)日：2018-06-12

申请号：US15117716

申请日：2014-03-12

Applicant: INTEL CORPORATION

Inventor： Thorsten Meyer ,  Gerald Ofner ,  Andreas Wolter ,  Georg Seidemann ,  Sven Albers ,  Christian Geissler

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L21/48 ,  H01L21/56 ,  H01L23/50 ,  H01L25/16 ,  H01L23/13

CPC classification number: H01L23/49838 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/565 ,  H01L23/13 ,  H01L23/3114 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/50 ,  H01L24/16 ,  H01L24/19 ,  H01L24/20 ,  H01L24/96 ,  H01L25/16 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16227 ,  H01L2224/24195 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2924/15151 ,  H01L2924/15159 ,  H01L2924/15174 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/1815 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105

Abstract: A microelectronic package including a passive microelectronic device disposed within a package body, wherein the package body is the portion of the microelectronic package which provides support and/or rigidity to the microelectronic package. In a flip-chip type microelectronic package, the package body may comprise a microelectronic substrate to which an active microelectronic device is electrically attached. In an embedded device type microelectronic package, the package body may comprise the material in which the active microelectronic device is embedded.

公开(公告)号：US20180150156A1

公开(公告)日：2018-05-31

申请号：US15879729

申请日：2018-01-25

Applicant: Intel Corporation

Inventor： Sven Albers ,  Klaus Reingruber ,  Teodora Ossiander ,  Andreas Wolter ,  Sonja Koller ,  Georg Seidemann ,  Jan Proschwitz ,  Hans-Joachim Barth ,  Bastiaan Elshof

IPC: G06F3/044 ,  G06F3/045 ,  G06F3/042 ,  G01L1/24 ,  G06F3/0354 ,  G06F3/038 ,  H04B1/3827 ,  G06F1/16

CPC classification number: G06F3/044 ,  G01L1/24 ,  G06F1/163 ,  G06F3/03547 ,  G06F3/038 ,  G06F3/042 ,  G06F3/045 ,  G06F2203/04102 ,  G06F2203/04109 ,  H04B1/385

Abstract: Some forms relate to wearable computing devices that include a “touch pad” like interface. In some forms, the example wearable computing devices may be integrated with (or attached to) textiles (i.e. clothing). In other forms, the example wearable computing devices may be attached directly to the skin of someone (i.e., similar to a bandage) that utilizes any of the example wearable computing devices. The example wearable computing devices include a flexible touch pad that may allow a user of the wearable computing device to more easily operate the wearable computing device. The example wearable computing devices described herein may include a variety of electronics. Some examples include a power supply and/or a communication device among other types of electronics.

公开(公告)号：US09653439B2

公开(公告)日：2017-05-16

申请号：US14778036

申请日：2014-12-09

Applicant: Intel Corporation

Inventor： Sven Albers ,  Andreas Wolter ,  Klaus Reingruber ,  Thorsten Meyer

IPC: H01L25/16 ,  H01L21/50 ,  H01L25/00 ,  H01L23/48 ,  H01L21/56 ,  H01L23/00 ,  H01L25/065 ,  H01L25/07 ,  H01L23/31 ,  H01L21/683 ,  H01L23/498 ,  H01L49/02

Abstract: A method including forming at least one passive structure on a substrate by a build-up process; introducing one or more integrated circuit chips on the substrate; and introducing a molding compound on the at least one passive structure and the one or more integrated circuit chips. A method including forming at least one passive structure on a substrate by a three-dimensional printing process; introducing one or more integrated circuit chips on the substrate; and embedding the at least one passive structure and the one or more integrated circuit chips in a molding compound. An apparatus including a package substrate including at least one three-dimensional printed passive structure and one or more integrated circuit chips embedded in a molding material.

公开(公告)号：US09343389B2

公开(公告)日：2016-05-17

申请号：US14827056

申请日：2015-08-14

Applicant: INTEL CORPORATION

Inventor： Michael P. Skinner ,  Teodora Ossiander ,  Sven Albers ,  Georg Seidemann

IPC: H01L23/32 ,  H01L23/498 ,  H01L25/065 ,  H01L25/00 ,  H01L23/00

CPC classification number: H01L25/0657 ,  H01F7/04 ,  H01L23/32 ,  H01L23/49811 ,  H01L23/49866 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L25/50 ,  H01L2224/10135 ,  H01L2224/10165 ,  H01L2224/11332 ,  H01L2224/11522 ,  H01L2224/132 ,  H01L2224/13298 ,  H01L2224/13355 ,  H01L2224/13357 ,  H01L2224/1336 ,  H01L2224/13444 ,  H01L2224/13464 ,  H01L2224/13469 ,  H01L2224/1601 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/811 ,  H01L2224/81139 ,  H01L2224/8114 ,  H01L2224/81193 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2225/06531 ,  H01L2225/06568 ,  H01L2225/06593 ,  H01L2225/06596 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2924/207 ,  H01L2924/00012

Abstract: Embodiments of the present disclosure are directed to integrated circuit (IC) package assemblies with magnetic contacts, as well as corresponding fabrication methods and systems incorporating such magnetic contacts. A first IC substrate may have a first magnet coupled with a first electrical routing feature. A second IC substrate may have a second magnet coupled with a second electrical routing feature. The magnets may be embedded in the IC substrates and/or electrical routing features. The magnets may generate a magnetic field that extends across a gap between the first and second electrical routing features. Electrically conductive magnetic particles may be applied to one or both of the IC substrates to form a magnetic interconnect structure that extends across the gap. In some embodiments, magnetic contacts may be demagnetized by heating the magnets to a corresponding partial demagnetization temperature (PDT) or Curie temperature. Other embodiments may be described and/or claimed.

公开(公告)号：US20150357311A1

公开(公告)日：2015-12-10

申请号：US14827056

申请日：2015-08-14

Applicant: INTEL CORPORATION

Inventor： Michael P. Skinner ,  Teodora Ossiander ,  Sven Albers ,  Georg Seidemann

IPC: H01L25/065

CPC classification number: H01L25/0657 ,  H01F7/04 ,  H01L23/32 ,  H01L23/49811 ,  H01L23/49866 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L25/50 ,  H01L2224/10135 ,  H01L2224/10165 ,  H01L2224/11332 ,  H01L2224/11522 ,  H01L2224/132 ,  H01L2224/13298 ,  H01L2224/13355 ,  H01L2224/13357 ,  H01L2224/1336 ,  H01L2224/13444 ,  H01L2224/13464 ,  H01L2224/13469 ,  H01L2224/1601 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/811 ,  H01L2224/81139 ,  H01L2224/8114 ,  H01L2224/81193 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2225/06531 ,  H01L2225/06568 ,  H01L2225/06593 ,  H01L2225/06596 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2924/207 ,  H01L2924/00012

Abstract: Embodiments of the present disclosure are directed to integrated circuit (IC) package assemblies with magnetic contacts, as well as corresponding fabrication methods and systems incorporating such magnetic contacts. A first IC substrate may have a first magnet coupled with a first electrical routing feature. A second IC substrate may have a second magnet coupled with a second electrical routing feature. The magnets may be embedded in the IC substrates and/or electrical routing features. The magnets may generate a magnetic field that extends across a gap between the first and second electrical routing features. Electrically conductive magnetic particles may be applied to one or both of the IC substrates to form a magnetic interconnect structure that extends across the gap. In some embodiments, magnetic contacts may be demagnetized by heating the magnets to a corresponding partial demagnetization temperature (PDT) or Curie temperature. Other embodiments may be described and/or claimed.

公开(公告)号：US11239199B2

公开(公告)日：2022-02-01

申请号：US15774906

申请日：2015-12-26

Applicant: Intel Corporation

Inventor： Georg Seidemann ,  Klaus Reingruber ,  Christian Geissler ,  Sven Albers ,  Andreas Wolter ,  Marc Dittes ,  Richard Patten

IPC: H01L23/48 ,  H01L23/52 ,  H01L25/065 ,  H01L23/00 ,  H01L25/00 ,  H01L23/498 ,  H01L21/48 ,  H01L23/31 ,  H01L23/538 ,  H01L21/56

Abstract: Embodiments are generally directed to package stacking using chip to wafer bonding. An embodiment of a device includes a first stacked layer including one or more semiconductor dies, components or both, the first stacked layer further including a first dielectric layer, the first stacked layer being thinned to a first thickness; and a second stacked layer of one or more semiconductor dies, components, or both, the second stacked layer further including a second dielectric layer, the second stacked layer being fabricated on the first stacked layer.

公开(公告)号：US09888577B2

公开(公告)日：2018-02-06

申请号：US14229476

申请日：2014-03-28

Applicant: INTEL CORPORATION

Inventor： Thorsten Meyer ,  Gerald Ofner ,  Sven Albers ,  Reinhard Mahnkopf

IPC: H05K1/18 ,  H01L23/498 ,  H01L23/522 ,  H01L23/66 ,  H05K1/02 ,  H01L23/00 ,  H05K1/16 ,  H05K3/46 ,  H01L21/56 ,  H01L25/065 ,  H01L25/16 ,  H01L25/18

CPC classification number: H05K1/181 ,  H01L21/568 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/5227 ,  H01L23/66 ,  H01L24/00 ,  H01L24/96 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/16 ,  H01L25/18 ,  H01L2224/04042 ,  H01L2224/12105 ,  H01L2224/16227 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06568 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/19011 ,  H01L2924/19105 ,  H05K1/0233 ,  H05K1/0292 ,  H05K1/162 ,  H05K1/165 ,  H05K1/185 ,  H05K3/4644 ,  H05K2201/10636 ,  H05K2203/1469 ,  H05K2203/171 ,  H05K2203/173 ,  H05K2203/175 ,  Y02P70/611 ,  H01L2924/00012 ,  H01L2924/00

Abstract: Passive electrical devices are described with a polymer carrier. In one example, a conductive layer is formed over a polymer substrate in a pattern to form a passive electrical device and at least two terminals of the device. A plurality of external connection pads are connected to the terminals of the device.

公开(公告)号：US20160358848A1

公开(公告)日：2016-12-08

申请号：US15117716

申请日：2014-03-12

Applicant: INTEL CORPORATION

Inventor： Thorsten Meyer ,  Gerald Ofner ,  Andreas Wolter ,  Georg Seidemann ,  Sven Albers ,  Christian Geissler

IPC: H01L23/498 ,  H01L21/56 ,  H01L21/48 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L23/49838 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/565 ,  H01L23/13 ,  H01L23/3114 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/50 ,  H01L24/16 ,  H01L24/19 ,  H01L24/20 ,  H01L24/96 ,  H01L25/16 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16227 ,  H01L2224/24195 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2924/15151 ,  H01L2924/15159 ,  H01L2924/15174 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/1815 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105

Abstract: A microelectronic package including a passive microelectronic device disposed within a package body, wherein the package body is the portion of the microelectronic package which provides support and/or rigidity to the microelectronic package. In a flip-chip type microelectronic package, the package body may comprise a microelectronic substrate to which an active microelectronic device is electrically attached. In an embedded device type microelectronic package, the package body may comprise the material in which the active microelectronic device is embedded.

Abstract translation: 一种微电子封装，包括设置在封装主体内的无源微电子器件，其中所述封装体是所述微电子封装的对所述微电子封装提供支撑和/或刚度的部分。 在倒装芯片型微电子封装中，封装主体可以包括微电子衬底，活性微电子器件电连接到微电子衬底。 在嵌入式设备型微电子封装中，封装体可以包括其中嵌入有源微电子器件的材料。

公开(公告)号：US09515049B2

公开(公告)日：2016-12-06

申请号：US14368434

申请日：2013-12-19

Applicant: Intel Corporation

Inventor： Sven Albers ,  Michael Skinner ,  Hans-Joachim Barth ,  Peter Baumgartner ,  Harald Gossner

IPC: H01L25/065 ,  H01L23/552 ,  H01L23/522 ,  H01L29/06 ,  H01L23/00 ,  H01L27/02

CPC classification number: H01L25/0652 ,  H01L23/367 ,  H01L23/3675 ,  H01L23/5226 ,  H01L23/5227 ,  H01L23/552 ,  H01L23/562 ,  H01L23/564 ,  H01L23/66 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/48 ,  H01L24/49 ,  H01L24/81 ,  H01L24/85 ,  H01L25/065 ,  H01L25/0657 ,  H01L27/0207 ,  H01L29/0657 ,  H01L2223/6677 ,  H01L2224/131 ,  H01L2224/1319 ,  H01L2224/16105 ,  H01L2224/16113 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/48091 ,  H01L2224/481 ,  H01L2224/48106 ,  H01L2224/4813 ,  H01L2224/48137 ,  H01L2224/48145 ,  H01L2224/48225 ,  H01L2224/48227 ,  H01L2224/48482 ,  H01L2224/49 ,  H01L2224/73257 ,  H01L2224/81001 ,  H01L2224/81007 ,  H01L2224/8114 ,  H01L2224/81801 ,  H01L2224/8185 ,  H01L2224/85801 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06551 ,  H01L2225/06589 ,  H01L2924/00014 ,  H01L2924/19104 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/014 ,  H01L2924/00012

Abstract: Embodiments of a flexibly-wrapped integrated circuit die device and a method for mounting a flexibly-wrapped integrated circuit die to a substrate are disclosed. In some embodiments, the flexibly-wrapped integrated circuit die device includes a substrate and a flexible integrated circuit die coupled to the substrate in a substantially vertical orientation with reference to a surface of the substrate.

Abstract translation: 公开了一种柔性包裹的集成电路管芯器件的实施例和用于将柔性封装的集成电路管芯安装到衬底的方法。 在一些实施例中，柔性包裹的集成电路管芯器件包括基板和柔性集成电路管芯，所述基板和基板相对于基板的表面以基本垂直的取向联接到基板。