公开(公告)号：US20240264530A1

公开(公告)日：2024-08-08

申请号：US18147472

申请日：2022-12-28

Applicant: Intel Corporation

Inventor： Ryan Carrazzone ,  Kyle Arrington ,  Brandon Rawlings ,  Bohan Shan ,  Dingying Xu

IPC: G03F7/16 ,  C08G75/20 ,  G03F7/038 ,  G03F7/039

CPC classification number: G03F7/168 ,  C08G75/20 ,  G03F7/038 ,  G03F7/039

Abstract: Light responsive photoresists, and methods of using light responsive photoresists in processes, such as lithography processes. The light responsive photoresists may include a polymer featuring a photocleavable group. Due to the photocleavable group, the polymer may depolymerize when irradiated with one or more wavelengths of light. The depolymerized products may be in the gas phase.

公开(公告)号：US12057369B2

公开(公告)日：2024-08-06

申请号：US18088478

申请日：2022-12-23

Applicant: Intel Corporation

Inventor： Weston Bertrand ,  Kyle Arrington ,  Shankar Devasenathipathy ,  Aaron McCann ,  Nicholas Neal ,  Zhimin Wan

IPC: H01L23/433 ,  H01L23/367 ,  H01L25/065

CPC classification number: H01L23/433 ,  H01L23/3675 ,  H01L25/0657

Abstract: Embodiments of the present disclosure may generally relate to systems, apparatuses, techniques, and/or processes directed to packages that include stacked dies that use thermal conductivity features including thermally conductive through silicon vias (TSVs) filled with thermally conductive material located in passive areas of a first die to route heat from a first die away from a second die that is coupled with the first die. In embodiments, the first die may be referred to as a base die. Embodiments may include thermal blocks in the form of dummy dies that include TSVs at least partially filled with thermal energy conducting material such as copper, solder, or other alloy.

公开(公告)号：US20240112971A1

公开(公告)日：2024-04-04

申请号：US17957359

申请日：2022-09-30

Applicant: Intel Corporation

Inventor： Yiqun Bai ,  Dingying Xu ,  Srinivas Pietambaram ,  Hongxia Feng ,  Gang Duan ,  Xiaoying Guo ,  Ziyin Lin ,  Bai Nie ,  Haobo Chen ,  Kyle Arrington ,  Bohan Shan

IPC: H01L23/15 ,  H01L21/02 ,  H01L23/495

CPC classification number: H01L23/15 ,  H01L21/02354 ,  H01L23/49506

Abstract: An integrated circuit (IC) device comprises a substrate comprising a glass core. The glass core comprises a first surface and a second surface opposite the first surface, and a first sidewall between the first surface and the second surface. The glass core may include a conductor within a through-glass via extending from the first surface to the second surface and a build-up layer. The glass cord comprises a plurality of first areas of the glass core and a plurality of laser-treated areas on the first sidewall. A first one of the plurality of laser-treated areas may be spaced away from a second one of the plurality of laser-treated areas. A first area may comprise a first nanoporosity and a laser-treated area may comprise a second nanoporosity, wherein the second nanoporosity is greater than the first nanoporosity.

公开(公告)号：US20240270929A1

公开(公告)日：2024-08-15

申请号：US18166005

申请日：2023-02-08

Applicant: Intel Corporation

Inventor： Clay Arrington ,  Kyle Arrington ,  Ziyin Lin ,  Jose Waimin ,  Dingying Xu

IPC: C08K3/04 ,  B82Y30/00 ,  B82Y40/00 ,  C08K9/04

CPC classification number: C08K3/041 ,  B82Y30/00 ,  B82Y40/00 ,  C08K9/04 ,  C08K2003/023 ,  C08K2201/011

Abstract: Capillary underfill formulations that may include fillers. The fillers may include carbon nanotubes, such as surface functionalized carbon nanotubes. Methods for forming capillary underfill materials that may have improved fracture toughness, reduced crack propagation, and a reduced likelihood of delamination. The surface functionalized carbon nanotubes may include amine functionalized carbon nanotubes. Containers, such as syringes, that may have a reservoir in which a capillary underfill formulation is disposed.

公开(公告)号：US20240222304A1

公开(公告)日：2024-07-04

申请号：US18148148

申请日：2022-12-29

Applicant: Intel Corporation

Inventor： Bohan Shan ,  Jiaqi Wu ,  Haobo Chen ,  Srinivas Pietambaram ,  Bai Nie ,  Gang Duan ,  Kyle Arrington ,  Ziyin Lin ,  Hongxia Feng ,  Yiqun Bai ,  Xiaoying Guo ,  Dingying Xu

IPC: H01L23/00 ,  H01L23/538

CPC classification number: H01L24/16 ,  H01L23/538 ,  H01L24/03 ,  H01L24/05 ,  H01L24/08 ,  H01L24/09 ,  H01L24/11 ,  H01L24/13 ,  H01L24/17 ,  H01L24/81 ,  H01L25/16

Abstract: Methods and apparatus to reduce solder bump bridging between two substrates. An apparatus includes a first substrate including a first bump and a second bump spaced apart from the first bump, the first bump including a first base, the second bump including a second base; and a second substrate including a third bump and a fourth bump spaced apart from the third bump, the third bump including a third base, the fourth bump including a fourth base, the first base electrically coupled to the third base by first solder, the second base electrically coupled to the fourth base by second solder, the first solder having a first volume, the second solder having a second volume, the first volume less than the second volume.

公开(公告)号：US20240213116A1

公开(公告)日：2024-06-27

申请号：US18069507

申请日：2022-12-21

Applicant: Intel Corporation

Inventor： Kyle Arrington ,  Bohan Shan ,  Haobo Chen ,  Ziyin Lin ,  Hongxia Feng ,  Yiqun Bai ,  Dingying Xu ,  Xiaoying Guo ,  Bai Nie ,  Srinivas Pietambaram ,  Gang Duan

IPC: H01L23/473 ,  H01L23/15 ,  H01L23/467 ,  H01L23/538

CPC classification number: H01L23/473 ,  H01L23/15 ,  H01L23/467 ,  H01L23/5383

Abstract: Methods, systems, apparatus, and articles of manufacture to cool integrated circuit packages having glass substrates are disclosed. An example glass core of an integrated circuit (IC) package disclosed herein includes a fluid inlet to receive a cooling fluid, a fluid outlet, and a channel to fluidly couple the fluid inlet to the fluid outlet, the cooling fluid to flow through the channel from the fluid inlet to the fluid outlet, the channel fluidly isolated from one or more vias extending between a first surface and a second surface of the glass core.

公开(公告)号：US11881438B2

公开(公告)日：2024-01-23

申请号：US16746732

申请日：2020-01-17

Applicant: Intel Corporation

Inventor： Elah Bozorg-Grayeli ,  Kyle Arrington ,  Sergio Chan Arguedas ,  Aravindha Antoniswamy

IPC: H01L23/373 ,  H01L23/367 ,  H01L23/16 ,  H01L23/00 ,  H01L21/48

CPC classification number: H01L23/3733 ,  H01L21/4853 ,  H01L21/4871 ,  H01L23/16 ,  H01L23/367 ,  H01L23/562 ,  H01L24/16 ,  H01L2224/16225 ,  H01L2924/3511

Abstract: A second-level thermal interface material (TIM2) that is to couple to a system-level thermal solution is applied to an integrated circuit (IC) assembly comprising an IC die and an assembly substrate prior to the assembly substrate being joined to a host component at the system-level. Challenges associated with TIM2 application may therefore be addressed at a first level of IC die integration, simplifying subsequent assembly and better controlling thermal coupling to a subsequently applied thermal solution. Where a first-level IC assembly includes a stiffener, the TIM may be affixed to the stiffener through an adhesive bond or a fusion bond. After the IC assembly including the TIM is soldered to the host board, a thermal solution may be placed in contact with the TIM. With early application of a solder TIM, a solder TIM may be reflowed upon the IC die multiple times.

公开(公告)号：US20210202348A1

公开(公告)日：2021-07-01

申请号：US16727770

申请日：2019-12-26

Applicant: Intel Corporation

Inventor： Kyle Arrington ,  Frederick Atadana ,  Taylor Gaines ,  Minseok Ha

IPC: H01L23/373 ,  H01L23/367 ,  H01L21/48

Abstract: An integrated circuit (IC) assembly comprising an IC die and a frame material that has been dispensed over the assembly substrate to be further adjacent to a perimeter edge of the IC die. The frame material may be selected to have flow properties that minimize slump, for example so a profile of a transverse cross-section through the frame material may retain convex curvature. The frame material may be cured following dispense, and upon application of a thermal interface material (TIM), the frame material may and act as a barrier, impeding flow of the TIM. The frame material may be compressed by force applied through an external thermal solution, such as a heat sink, to ensure good contact to the TIM.

公开(公告)号：US12266589B2

公开(公告)日：2025-04-01

申请号：US18635894

申请日：2024-04-15

Applicant: Intel Corporation

Inventor： Weston Bertrand ,  Kyle Arrington ,  Shankar Devasenathipathy ,  Aaron McCann ,  Nicholas Neal ,  Zhimin Wan

IPC: H01L23/433 ,  H01L23/367 ,  H01L25/065

Abstract: Embodiments of the present disclosure may generally relate to systems, apparatuses, techniques, and/or processes directed to packages that include stacked dies that use thermal conductivity features including thermally conductive through silicon vias (TSVs) filled with thermally conductive material located in passive areas of a first die to route heat from a first die away from a second die that is coupled with the first die. In embodiments, the first die may be referred to as a base die. Embodiments may include thermal blocks in the form of dummy dies that include TSVs at least partially filled with thermal energy conducting material such as copper, solder, or other alloy.

公开(公告)号：US20240312865A1

公开(公告)日：2024-09-19

申请号：US18182879

申请日：2023-03-13

Applicant: Intel Corporation

Inventor： Kyle Arrington ,  Bohan Shan ,  Haobo Chen ,  Bai Nie ,  Srinivas Pietambaram ,  Gang Duan ,  Ziyin Lin ,  Hongxia Feng ,  Yiqun Bai ,  Xiaoying Guo ,  Dingying Xu

IPC: H01L23/373 ,  H01L21/48 ,  H01L23/498

CPC classification number: H01L23/3733 ,  H01L21/486 ,  H01L23/49827 ,  H01L23/49866 ,  H01L23/49877 ,  H01L23/15

Abstract: Methods, systems, apparatus, and articles of manufacture to improve reliability of vias in a glass substrate of an integrated circuit package are disclosed. An example integrated circuit (IC) package substrate includes a glass substrate, a via extending between first and second surfaces of the glass substrate, and a conductive material provided in the via, the conductive material including gallium and silver.