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公开(公告)号:US09461010B2
公开(公告)日:2016-10-04
申请号:US14997919
申请日:2016-01-18
Applicant: Intel Corporation
Inventor: Qing Ma , Jun He , Patrick Morrow , Paul B. Fischer , Sridhar Balakrishnan , Satish Radhakrishnan , Tatyana Andryushchenko , Guanghai Xu
IPC: H05K1/03 , H01L23/00 , B23K1/00 , H05K3/40 , H01L21/033
CPC classification number: H01L24/19 , B23K1/0016 , H01L21/0334 , H01L24/11 , H01L2224/245 , H01L2924/01322 , H01L2924/14 , H05K3/4015 , H05K2201/1028 , H01L2924/00
Abstract: The present subject matter relates to the field of fabricating microelectronic devices. In at least one embodiment, the present subject matter relates to forming an interconnect that has a portion thereof which becomes debonded from the microelectronic device during cooling after attachment to an external device. The debonded portion allows the interconnect to flex and absorb stress.
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公开(公告)号:US10204855B2
公开(公告)日:2019-02-12
申请号:US14653033
申请日:2014-07-11
Applicant: Intel Corporation
Inventor: Alejandro Levander , Tatyana Andryushchenko , David Staines , Mauro Kobrinsky , Aleksandar Aleksov , Dilan Seneviratne , Javier Soto Gonzalez , Srinivas Pietambaram , Rafiqul Islam
IPC: H01L23/00 , H01L23/498 , B23B5/16 , B32B27/08 , B32B27/28 , H01L21/48 , H01L21/56 , H01L21/683 , H01L21/78 , H01L23/31 , H01L25/00 , H05K1/02
Abstract: Generally discussed herein are systems and methods that can include a stretchable and bendable device. According to an example a method can include (1) depositing a first elastomer material on a panel, (2) laminating trace material on the elastomer material, (3) processing the trace material to pattern the trace material into one or more traces and one or more bond pads, (4) attaching a die to the one or more bond pads, or (5) depositing a second elastomer material on and around the one or more traces, the bonds pads, and the die to encapsulate the one or more traces and the one or more bond pads in the first and second elastomer materials.
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3.
公开(公告)号:US20160284630A1
公开(公告)日:2016-09-29
申请号:US14653033
申请日:2014-07-11
Applicant: INTEL CORPORATION
Inventor: Alejandro Levander , Tatyana Andryushchenko , David Staines , Mauro Kobrinsky , Aleksandar Aleksov , Dilan Seneviratne , Javier Soto Gonzalez , Srinivas Pietambaram , Rafiqul Islam
IPC: H01L23/498 , H01L21/56 , H01L25/00 , H01L23/31 , H01L21/78 , H01L21/683 , H01L21/48 , H01L23/00
CPC classification number: H01L23/4985 , B23B5/16 , B32B27/08 , B32B27/283 , B32B2307/54 , B32B2307/7265 , B32B2439/00 , B32B2457/00 , H01L21/4846 , H01L21/561 , H01L21/565 , H01L21/568 , H01L21/6835 , H01L21/78 , H01L23/3135 , H01L23/49811 , H01L23/49838 , H01L23/49866 , H01L23/49894 , H01L24/48 , H01L24/85 , H01L24/96 , H01L25/50 , H01L2221/68345 , H01L2221/68381 , H01L2224/48227 , H01L2224/81192 , H01L2224/81203 , H01L2224/81815 , H01L2224/85801 , H01L2924/00014 , H01L2924/01013 , H01L2924/01022 , H01L2924/01024 , H01L2924/01029 , H01L2924/01079 , H01L2924/0715 , H01L2924/15747 , H01L2924/15791 , H05K1/0283 , H01L2224/45099 , H01L2224/45015 , H01L2924/207 , H01L2224/85399 , H01L2224/05599
Abstract: Generally discussed herein are systems and methods that can include a stretchable and bendable device. According to an example a method can include (1) depositing a first elastomer material on a panel, (2) laminating trace material on the elastomer material, (3) processing the trace material to pattern the trace material into one or more traces and one or more bond pads, (4) attaching a die to the one or more bond pads, or (5) depositing a second elastomer material on and around the one or more traces, the bonds pads, and the die to encapsulate the one or more traces and the one or more bond pads in the first and second elastomer materials.
Abstract translation: 这里通常讨论的是可以包括可拉伸和可弯曲装置的系统和方法。 根据一个实例,一种方法可以包括(1)在面板上沉积第一弹性体材料,(2)在弹性体材料上层叠微量材料,(3)处理微量材料以将痕量材料图案化成一个或多个迹线 或更多的接合垫,(4)将管芯附接到所述一个或多个接合焊盘,或(5)在所述一个或多个迹线上和周围沉积第二弹性体材料,所述接合焊盘和所述管芯以将所述一个或多个 迹线和第一和第二弹性体材料中的一个或多个接合焊盘。
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4.
公开(公告)号:US09391019B2
公开(公告)日:2016-07-12
申请号:US14220814
申请日:2014-03-20
Applicant: Intel Corporation
Inventor: Mauro Kobrinsky , Tatyana Andryushchenko , Ramanan Chebiam , Hui Jae Yoo
IPC: H01L23/48 , H01L23/522 , H01L21/768 , H01L23/532
CPC classification number: H01L23/5226 , H01L21/76805 , H01L21/76814 , H01L21/76816 , H01L21/76826 , H01L21/76831 , H01L21/76843 , H01L21/76874 , H01L21/76879 , H01L21/76885 , H01L21/76895 , H01L21/76897 , H01L23/53223 , H01L23/53238 , H01L23/53252 , H01L23/53266 , H01L23/53295 , H01L2924/0002 , H01L2924/00
Abstract: Interconnect structures including a selective via post disposed on a top surface of a lower level interconnect feature, and fabrication techniques to selectively form such a post. Following embodiments herein, a minimum interconnect line spacing may be maintained independent of registration error in a via opening. In embodiments, a selective via post has a bottom lateral dimension smaller than that of a via opening within which the post is disposed. Formation of a conductive via post may be preferential to a top surface of the lower interconnect feature exposed by the via opening. A subsequently deposited dielectric material backfills portions of a via opening extending beyond the interconnect feature where no conductive via post was formed. An upper level interconnect feature is landed on the selective via post to electrically interconnect with the lower level feature.
Abstract translation: 互连结构,包括设置在下层互连特征的顶表面上的选择通孔,以及选择性地形成这种柱的制造技术。 以下实施例中,可以独立于通孔开口中的配准误差来维持最小互连线间距。 在实施例中,选择性通孔支柱的底部横向尺寸小于通孔开口的底部横向尺寸,在该通孔开口内设置有支柱。 导电通孔的形成可优先于由通孔开口暴露的下互连特征的顶表面。 随后沉积的电介质材料回填了超过互连特征的通孔开口的部分,其中没有形成导电通孔。 上级互连功能着陆在选择性通孔上以与较低级别特征电互连。
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公开(公告)号:US20160133596A1
公开(公告)日:2016-05-12
申请号:US14997919
申请日:2016-01-18
Applicant: Intel Corporation
Inventor: Qing Ma , Jun He , Patrick Morrow , Paul B. Fischer , Sridhar Balakrishnan , Satish Radhakrishnan , Tatyana Andryushchenko , Guanghai Xu
IPC: H01L23/00 , H01L21/033
CPC classification number: H01L24/19 , B23K1/0016 , H01L21/0334 , H01L24/11 , H01L2224/245 , H01L2924/01322 , H01L2924/14 , H05K3/4015 , H05K2201/1028 , H01L2924/00
Abstract: The present subject matter relates to the field of fabricating microelectronic devices. In at least one embodiment, the present subject matter relates to forming an interconnect that has a portion thereof which becomes debonded from the microelectronic device during cooling after attachment to an external device. The debonded portion allows the interconnect to flex and absorb stress.
Abstract translation: 本主题涉及制造微电子器件的领域。 在至少一个实施例中,本主题涉及形成具有其部分的互连,其在附接到外部设备之后在冷却期间从微电子器件脱粘。 脱粘部分允许互连件弯曲并吸收应力。
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