公开(公告)号：US20250113580A1

公开(公告)日：2025-04-03

申请号：US18374528

申请日：2023-09-28

Applicant: Intel Corporation

Inventor： Leonard Guler ,  Shaun Mills ,  Joseph D'Silva ,  Ehren Mannebach ,  Mauro Kobrinsky ,  Charles H. Wallace ,  Kalpesh Mahajan ,  Vivek Vishwakarma ,  Dincer Unluer ,  Jessica Panella

IPC: H01L29/417 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786

Abstract: Devices, transistor structures, systems, and techniques are described herein related to contacting source and drain transistor structures from the device backside at small dimensions and cell sizes. A first subset of dummy contact structures are removed and backfilled with contact metal and a first etch stop material. A second subset of dummy contact structures are removed and backfilled with contact metal and a second etch stop material. Subsequent metallization contacts to the first and second contacts are made using two masking/selective etch processes such that any misalignment to the other contact type does not allow contact due to the pertinent etch stop material.

公开(公告)号：US11721554B2

公开(公告)日：2023-08-08

申请号：US16356402

申请日：2019-03-18

Applicant: Intel Corporation

Inventor： Anant Jahagirdar ,  Chytra Pawashe ,  Aaron Lilak ,  Myra McDonnell ,  Brennen Mueller ,  Mauro Kobrinsky

IPC: H01L29/78 ,  H01L29/10 ,  H01L29/66 ,  H01L29/161 ,  H01L21/20 ,  H01L21/56 ,  H01L21/02 ,  H01L21/603

CPC classification number: H01L21/2007 ,  H01L21/0226 ,  H01L21/56 ,  H01L21/603

Abstract: Embodiments herein describe techniques for bonded wafers that includes a first wafer bonded with a second wafer, and a stress compensation layer in contact with the first wafer or the second wafer. The first wafer has a first stress level at a first location, and a second stress level different from the first stress level at a second location. The stress compensation layer includes a first material at a first location of the stress compensation layer that induces a third stress level at the first location of the first wafer, a second material different from the first material at a second location of the stress compensation layer that induces a fourth stress level different from the third stress level at the second location of the first wafer. Other embodiments may be described and/or claimed.

公开(公告)号：US20220059702A1

公开(公告)日：2022-02-24

申请号：US17517583

申请日：2021-11-02

Applicant: Intel Corporation

Inventor： Carl Naylor ,  Abhishek Sharma ,  Mauro Kobrinsky ,  Christopher Jezewski ,  Urusa Alaan ,  Justin Weber

IPC: H01L29/786 ,  H01L29/66 ,  H01L27/12

Abstract: Transistor structures with a channel semiconductor material that is passivated with two-dimensional (2D) crystalline material. The 2D material may comprise a semiconductor having a bandgap offset from a band of the channel semiconductor. The 2D material may be a thin as a few monolayers and have good temperature stability. The 2D material may be a conversion product of a sacrificial precursor material, or of a portion of the channel semiconductor material. The 2D material may comprise one or more metal and a chalcogen. The channel material may be a metal oxide semiconductor suitable for low temperature processing (e.g., IGZO), and the 2D material may also be compatible with low temperature processing (e.g.,

公开(公告)号：US11018075B2

公开(公告)日：2021-05-25

申请号：US16221815

申请日：2018-12-17

Applicant: Intel Corporation

Inventor： Carl Naylor ,  Ashish Agrawal ,  Kevin Lin ,  Abhishek Sharma ,  Mauro Kobrinsky ,  Christopher Jezewski ,  Urusa Alaan

IPC: H01L27/12 ,  H01L23/40 ,  H01L21/822 ,  H01L23/532 ,  H01L21/70

Abstract: An example relates to an integrated circuit including a semiconductor substrate, and a wiring layer stack located on the semiconductor substrate. The integrated circuit further includes a transistor embedded in the wiring layer stack. The transistor includes an embedded layer. The embedded layer has a thickness of less than 10 nm. The embedded layer includes at least one two-dimensional crystalline layer including more than 10% metal atoms. Further examples relate to methods for forming integrated circuits.

公开(公告)号：US20210098387A1

公开(公告)日：2021-04-01

申请号：US16585666

申请日：2019-09-27

Applicant: Intel Corporation

Inventor： Carl Naylor ,  Mauro Kobrinsky ,  Richard Vreeland ,  Ramanan Chebiam ,  William Brezinski ,  Brennen Mueller ,  Jeffery Bielefeld

IPC: H01L23/532 ,  H01L21/768

Abstract: Composite integrated circuit (IC) device structures that include two components coupled through a hybrid bonded composite interconnect structure. The two components may be two different monolithic IC structures (e.g., chips) that are bonded over substantially planar dielectric and metallization interfaces. Composite interconnect metallization features formed at a bond interface may be doped with a metal or chalcogenide dopant. The dopant may migrate to a periphery of the composite interconnect structure and form a barrier material that will then limit outdiffusion of a metal, such as copper, into adjacent dielectric material.

公开(公告)号：US11985909B2

公开(公告)日：2024-05-14

申请号：US16435875

申请日：2019-06-10

Applicant: Intel Corporation

Inventor： Elijah Karpov ,  Mauro Kobrinsky

IPC: G11C11/00 ,  G11C13/00 ,  H10B63/00 ,  H10N70/00 ,  H10N70/20

CPC classification number: H10N70/231 ,  G11C13/0004 ,  G11C13/0069 ,  G11C13/0097 ,  H10B63/20 ,  H10B63/24 ,  H10B63/30 ,  H10N70/826 ,  H10N70/841 ,  H10N70/8828 ,  G11C13/004 ,  G11C2013/0092 ,  G11C2213/52 ,  G11C2213/72 ,  G11C2213/79

Abstract: Embodiments disclosed herein include memory bitcells and methods of forming such memory bitcells. In an embodiment, the memory bitcell is part of an embedded DRAM (eDRAM) memory device. In an embodiment, the memory bitcell comprises a substrate and a storage element embedded in the substrate. In an embodiment, the storage element comprises a phase changing material that comprises a binary alloy. In an embodiment, the memory bitcell further comprises a first electrode over a first surface of the storage element, and a second electrode over a second surface of the storage element.

公开(公告)号：US11532558B2

公开(公告)日：2022-12-20

申请号：US16585666

申请日：2019-09-27

Applicant: Intel Corporation

Inventor： Carl Naylor ,  Mauro Kobrinsky ,  Richard Vreeland ,  Ramanan Chebiam ,  William Brezinski ,  Brennen Mueller ,  Jeffery Bielefeld

IPC: H01L23/532 ,  H01L21/768

Abstract: Composite integrated circuit (IC) device structures that include two components coupled through a hybrid bonded composite interconnect structure. The two components may be two different monolithic IC structures (e.g., chips) that are bonded over substantially planar dielectric and metallization interfaces. Composite interconnect metallization features formed at a bond interface may be doped with a metal or chalcogenide dopant. The dopant may migrate to a periphery of the composite interconnect structure and form a barrier material that will then limit outdiffusion of a metal, such as copper, into adjacent dielectric material.

公开(公告)号：US11164809B2

公开(公告)日：2021-11-02

申请号：US16221815

申请日：2018-12-17

Applicant: Intel Corporation

Inventor： Carl Naylor ,  Ashish Agrawal ,  Kevin Lin ,  Abhishek Sharma ,  Mauro Kobrinsky ,  Christopher Jezewski ,  Urusa Alaan

IPC: H01L27/12 ,  H01L23/40 ,  H01L21/70 ,  H01L21/822 ,  H01L23/532

Abstract: An example relates to an integrated circuit including a semiconductor substrate, and a wiring layer stack located on the semiconductor substrate. The integrated circuit further includes a transistor embedded in the wiring layer stack. The transistor includes an embedded layer. The embedded layer has a thickness of less than 10 nm. The embedded layer includes at least one two-dimensional crystalline layer including more than 10% metal atoms. Further examples relate to methods for forming integrated circuits.

公开(公告)号：US12211794B2

公开(公告)日：2025-01-28

申请号：US17648821

申请日：2022-01-25

Applicant: Intel Corporation

Inventor： Carl Naylor ,  Ashish Agrawal ,  Kevin Lin ,  Abhishek Anil Sharma ,  Mauro Kobrinsky ,  Christopher Jezewski ,  Urusa Alaan

IPC: H01L23/532 ,  H01L21/02 ,  H01L21/768 ,  H01L23/522 ,  H01L29/24 ,  H01L29/45 ,  H01L29/66 ,  H01L29/786 ,  H01L21/285

Abstract: An aspect of the disclosure relates to an integrated circuit. The integrated circuit includes a first electrically conductive structure, a thin film crystal layer located on the first electrically conductive structure, and a second electrically conductive structure including metal e.g. copper. The second electrically conductive structure is located on the thin film crystal layer. The first electrically conductive structure is electrically connected to the second electrically conductive structure through the thin film crystal layer. The thin film crystal layer may be provided as a copper diffusion barrier.

公开(公告)号：US11948874B2

公开(公告)日：2024-04-02

申请号：US16914132

申请日：2020-06-26

Applicant: Intel Corporation

Inventor： Kevin L. Lin ,  Sukru Yemenicioglu ,  Patrick Morrow ,  Richard Schenker ,  Mauro Kobrinsky

IPC: H01L23/498 ,  H01L21/768 ,  H01L27/088 ,  H05K1/11 ,  H05K3/00 ,  H05K3/40

CPC classification number: H01L23/49827 ,  H01L21/76879 ,  H01L27/088 ,  H05K1/115 ,  H05K3/0094 ,  H05K3/4038

Abstract: An integrated circuit interconnect level including a lower metallization line vertically spaced from upper metallization lines. Lower metallization lines may be self-aligned to upper metallization lines enabling increased metallization line width without sacrificing line density for a given interconnect level. Combinations of upper and lower metallization lines within an interconnect metallization level may be designed to control intra-layer resistance/capacitance of integrated circuit interconnect. Dielectric material between two adjacent co-planar metallization lines may be recessed or deposited selectively to the metallization lines. Supplemental metallization may then be deposited and planarized. A top surface of the supplemental metallization may either be recessed to form lower metallization lines between upper metallization lines, or planarized with dielectric material to form upper metallization lines between lower metallization lines. Vias to upper and lower metallization line may extend another metallization level.