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公开(公告)号：US20220209794A1
公开(公告)日：2022-06-30
申请号：US17700022
申请日：2022-03-21
Applicant: Intel Corporation
Inventor： Poovaiah M. PALANGAPPA , Zion S. KWOK , Ravi H. MOTWANI
Abstract: A memory controller system includes error correction circuitry and erasure decoder circuitry. A retry flow is triggered when the memory controller's error checking and correction (ECC) detects an uncorrectable codeword. Error correction circuitry generates erasure codewords from the codeword with uncorrectable errors. The memory controller computes the syndrome weight of the erasure codewords. For example, the erasure decoder circuitry receives the erasure codewords and computes the syndrome weights. Error correction circuitry orders the erasure codewords based on their corresponding syndrome weights. Then error correction circuitry selects a subset of the codewords, and sends them to erasure decoder circuitry. Erasure decoder circuitry receives the selected codewords and decodes them.
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2.发明申请公开(公告)号：US20200219580A1
公开(公告)日：2020-07-09
申请号：US16827235
申请日：2020-03-23
Applicant: Intel Corporation
Inventor： Jawad B. KHAN , Richard L. COULSON , Zion S. KWOK , Ravi H. MOTWANI
IPC: G11C29/42 , G11C29/44 , G11C29/02 , G11C11/409 , G11C5/02
Abstract: Error correction values for a memory device include row error correction values and column error correction values for the same memory array. The memory device includes a memory array that is addressable in two spatial dimensions: a row dimension and a column dimension. The memory array is written as rows of data, and can be read as rows in the row dimension or read as columns in the column dimension. A data write triggers updates to row error correction values and to column error correction values.
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公开(公告)号：US20250123921A1
公开(公告)日：2025-04-17
申请号：US18999443
申请日：2024-12-23
Applicant: Intel Corporation
Inventor： Zion S. KWOK
IPC: G06F11/10
Abstract: A memory subsystem performs error correction through erasure decoding instead of ECC (error correction code) polynomial computation. An error correction module of the memory controller receives a data word and calculates a syndrome using the data word. The error correction module generates multiple correctable error pattern candidates for bounded fault regions based on erasure decoding. The error correction module selects one correctable error pattern candidate to apply error correction.
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4.发明申请公开(公告)号：US20190004893A1
公开(公告)日：2019-01-03
申请号：US15636635
申请日：2017-06-28
Applicant: INTEL CORPORATION
Inventor： Zion S. KWOK , Santhosh K. VANAPARTHY , Ravi H. MOTWANI
CPC classification number: G06F11/106 , G06F11/1012 , G06F11/1072 , G11C11/5628 , G11C16/10 , G11C16/3418 , G11C16/3431 , G11C16/3459
Abstract: Provided are an apparatus, non-volatile memory storage device and method for detecting drift in in non-volatile memory. A determination is made as to whether bits to write have more of a first value than a second value. Each of the bits are flipped to another of the first or second value when the bits have more of the first value than the second value. Indication is made whether the bits were flipped or not flipped. Parity is calculated for the bits and the bits and the parity for the bits are written to a location in the non-volatile memory. The bits at the location in the non-volatile memory are read and each of the bits having the first value are flipped to the second value and each of the bits having the second value are flipped to the first value in response to indication that the bits were flipped.
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公开(公告)号：US20170300380A1
公开(公告)日：2017-10-19
申请号：US15438655
申请日：2017-02-21
Applicant: INTEL CORPORATION
Inventor： Andre LEI , Scott NELSON , Zion S. KWOK , Ravi H. MOTWANI
CPC classification number: G06F11/1068 , G06F11/1012 , G11C5/143 , G11C29/52 , H03M13/098 , H03M13/1105 , H03M13/2906 , H03M13/3715
Abstract: Provided are a method, system, and apparatus using reliability information from multiple storage units and a parity storage unit to recover data for a failed one of the storage units. A decoding operation of the codeword is performed in each of the storage units comprising the data storage units other than the target data storage unit and the parity storage unit to produce reliability information. In response to the decoding operation failing for at least one additional failed storage unit comprising the data and/or parity storage units other than the target data storage unit that failed to decode, reliability information is obtained for the data portion of the at least one additional failed storage unit. The reliability information obtained from the storage units other than the target data storage unit is used to produce corrected data for the data unit in the target data storage unit.
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Patent Agency Ranking
6.发明申请公开(公告)号：US20190238158A1
公开(公告)日：2019-08-01
申请号：US16370178
申请日：2019-03-29
Applicant: Intel Corporation
Inventor： Aman BHATIA , Zion S. KWOK , Justin KANG , Poovaiah M. PALANGAPPA , Santhosh K. VANAPARTHY
CPC classification number: H03M13/1108 , G06F11/1068 , G11C29/52
Abstract: Examples include techniques to use intrinsic information when implementing a bit-flipping algorithm. An error correction control (ECC) decoder uses the intrinsic information to decode a low density parity count (LDPC) codeword. The intrinsic information including bits of a copy of a received LDPC codeword are compared to bits for variable nodes during an iteration of the bit-flipping algorithm to aid a determination as whether one or more bits for the variable nodes are to be flipped.
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公开(公告)号：US20190043589A1
公开(公告)日：2019-02-07
申请号：US15948556
申请日：2018-04-09
Applicant: Intel Corporation
Inventor： Zion S. KWOK , Pranav KALAVADE , Ravi H. MOTWANI
Abstract: One-sided soft reads can enable improved error-correction over regular reads without significantly increasing the latency for reads. In one example, a flash storage device includes an array of storage cells and a controller to access the array of storage cells. The controller is to perform at least one read of a storage cell to cause a read strobe to be applied at an expected read reference voltage and also cause one or more additional read strobes to be applied of the at voltages on only one side of the expected read reference voltage (e.g., which in some cases involves applying the additional one or more read strobes at a voltage with a slightly lower or higher magnitude than the magnitude of the expected read reference voltage). The controller can then provide a logic value and one or more bits indicating confidence or reliability of the logic value's accuracy based on an electrical response of the storage cell to the read strobe and the one or more additional read strobes.
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8.发明申请USING RELIABILITY INFORMATION FROM MULTIPLE STORAGE UNITS AND A PARITY STORAGE UNIT TO RECOVER DATA FOR A FAILED ONE OF THE STORAGE UNITS 有权使用来自多个存储单元和存储单元的可靠性信息来恢复存储单元中的一个存储单元的数据公开(公告)号：US20160092300A1
公开(公告)日：2016-03-31
申请号：US14499078
申请日：2014-09-26
Applicant: INTEL CORPORATION
Inventor： Andre LEI , Scott NELSON , Zion S. KWOK , Ravi H. MOTWANI
CPC classification number: G06F11/1068 , G06F11/1012 , G11C5/143 , G11C29/52 , H03M13/1105
Abstract: Provided are a method, system, and apparatus using reliability information from multiple storage units and a parity storage unit to recover data for a failed one of the storage units. A decoding operation of the codeword is performed in each of the storage units comprising the data storage units other than the target data storage unit and the parity storage unit to produce reliability information. In response to the decoding operation failing for at least one additional failed storage unit comprising the data and/or parity storage units other than the target data storage unit that failed to decode, reliability information is obtained for the data portion of the at least one additional failed storage unit. The reliability information obtained from the storage units other than the target data storage unit is used to produce corrected data for the data unit in the target data storage unit.
Abstract translation: 提供了使用来自多个存储单元的可靠性信息和奇偶校验存储单元来恢复存储单元中的一个故障存储单元的数据的方法，系统和装置。 在包括目标数据存储单元和奇偶校验存储单元以外的数据存储单元的每个存储单元中执行码字的解码操作，以产生可靠性信息。 响应于对于至少一个附加的故障存储单元的解码操作失败，所述至少一个附加故障存储单元包括除了解码失败的目标数据存储单元之外的数据和/或奇偶校验存储单元，对于至少一个附加的数据部分的数据部分获得可靠性信息 存储单元故障 从目标数据存储单元以外的存储单元获得的可靠性信息用于生成目标数据存储单元中的数据单元的校正数据。
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公开(公告)号：US20220415425A1
公开(公告)日：2022-12-29
申请号：US17358421
申请日：2021-06-25
Applicant: Intel Corporation
Inventor： Hemant P. RAO , Raymond W. ZENG , Prashant S. DAMLE , Zion S. KWOK , Kiran PANGAL , Mase J. TAUB
Abstract: A read technique for both SLC (single level cell) and MLC (multi-level cell) cross-point memory can mitigate drift-related errors with minimal or no drift tracking. In one example, a read at a higher magnitude voltage is applied first, which causes the drift for cells in a lower threshold voltage state to be reset. In one example, the read at the first voltage can be a full float read to minimize disturb. A second read can then be performed at a lower voltage without the need to adjust the read voltage due to drift.
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公开(公告)号：US20210013903A1
公开(公告)日：2021-01-14
申请号：US17032567
申请日：2020-09-25
Applicant: Intel Corporation
Inventor： Santhosh K. VANAPARTHY , Zion S. KWOK , Ravi H. MOTWANI
Abstract: Examples include techniques to improve error correction using an exclusive OR (XOR) rebuild scheme that includes two uncorrectable codewords. Examples include generation of soft XOR codewords using bits of correctable codewords to rebuild a codeword read from a memory that has uncorrectable errors and adjust bit reliability information to generate a new codeword having correctable errors. Examples also include techniques to prevent mis-correction due to read reference voltage shifts using non-linear transformations.
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