公开(公告)号：US20030100190A1

公开(公告)日：2003-05-29

申请号：US09994340

申请日：2001-11-26

Applicant: International Business Machines Corporation

Inventor： William J. Cote ,  Timothy J. Dalton ,  Prakash Chimanlal Dev ,  Daniel C. Edelstein ,  Scott D. Halle ,  Gill Yong Lee ,  Arpan P. Mahorowala

IPC: H01L021/461 ,  H01L021/302

CPC classification number: H01L21/76808 ,  H01L21/31633

Abstract: A process for forming a damascene structure includes depositing a bilayer comprising a first dielectric layer and a second dielectric layer onto a substrate, wherein the first layer has a dielectric constant higher than the second layer, and wherein the second layer is selected from a low k dielectric material comprising Si, C, O and H. The multi-step damascene structure is patterned into the dielectric bilayer using highly selective anisotropic reactive ion etching. Photoresist, polymers and post etch residues are removed from the substrate using a plasma ashing process without damaging the underlying dielectric layers.

公开(公告)号：US20020066234A1

公开(公告)日：2002-06-06

申请号：US10051135

申请日：2002-01-18

Applicant: International Business Machines Corporation

Inventor： William J. Cote ,  Daniel C. Edelstein ,  Naftali E. Lustig

IPC: C09C001/68 ,  C09K003/14

CPC classification number: H01L21/76843 ,  C09G1/02 ,  C23F3/00 ,  H01L21/3212 ,  H01L21/7684

Abstract: A tantalum-based liner for copper metallurgy is selectively removed by chemical-mechanical planarization (CMP) in an acidic slurry of an oxidizer such as hydrogen peroxide, deionized water, a corrosion inhibitor such as BTA, and a surfactant such as Duponol SP, resulting in a high removal rate of the liner without appreciable removal of the exposed copper and with minimal dishing.

Abstract translation: 通过化学机械平面化（CMP）在氧化剂如过氧化氢，去离子水，腐蚀抑制剂如BTA的酸性浆料和诸如Duponol SP的表面活性剂中选择性地除去用于铜冶金的钽基衬垫，得到 在较高的衬里去除速率下，无明显去除暴露的铜和最小的凹陷。

公开(公告)号：US20030087043A1

公开(公告)日：2003-05-08

申请号：US10005861

申请日：2001-11-08

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Daniel C. Edelstein ,  William J. Cote ,  Timothy J. Dalton ,  Christopher V. Jahnes ,  Gill Young Lee

IPC: C23C016/00

CPC classification number: C23C16/30 ,  C23C16/505

Abstract: A process of depositing a low k dielectric film on a substrate includes using plasma enhance chemical vapor deposition to deposit a hydrogenated oxidized silicon carbon film. The process includes flowing a precursor gas containing Si, C, H and an oxygen-providing gas into the PECVD chamber. The precursor gas and the oxygen-providing gas are substantially free from nitrogen. The oxygen-providing gas is selected from the group consisting of oxygen, carbon monoxide, carbon dioxide, ozone, water vapor and a combination of at least one of the foregoing.

Abstract translation: 在衬底上沉积低k电介质膜的工艺包括使用等离子体增强化学气相沉积来沉积氢化的氧化硅碳膜。 该方法包括使含有Si，C，H和氧供给气体的前体气体流入PECVD室。 前体气体和供氧气体基本上不含氮气。 供氧气体选自氧气，一氧化碳，二氧化碳，臭氧，水蒸汽以及前述的至少一种的组合。

公开(公告)号：US20030032306A1

公开(公告)日：2003-02-13

申请号：US09928209

申请日：2001-08-10

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Richard A. Conti ,  Daniel C. Edelstein ,  Gill Yong Lee

IPC: H01L021/469 ,  H01L021/31

CPC classification number: H01L21/02271 ,  C23C16/401 ,  H01L21/02112 ,  H01L21/02129 ,  H01L21/02205 ,  H01L21/02216 ,  H01L21/3122 ,  H01L21/31604 ,  H01L21/31625 ,  H01L21/31629 ,  H01L21/31633 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method is described for forming a low-k dielectric film, in particular, a pre-metal dielectric (PMD) on a semiconductor wafer which has good gap-filling characteristics. The method uses a thermal sub-atmospheric CVD process that includes a carbon-containing organometallic precusor such as TMCTS or OMCTS, an ozone-containing gas, and a source of dopants for gettering alkali elements and for lowering the reflow temperature of the dielectric while attaining the desired low-k and gap-filling properties of the dielectric film. Phosphorous is a preferred dopant for gettering alkali elements such as sodium. Additional dopants for lowering the reflow temperature include, but are not limited to boron, germanium, arsenic, fluorine or combinations thereof.

Abstract translation: 描述了一种形成低k电介质膜的方法，特别是在具有良好间隙填充特性的半导体晶片上的预金属电介质（PMD）。 该方法使用包括含碳有机金属预处理剂如TMCTS或OMCTS，含臭氧气体和用于吸收碱元素的掺杂剂源的热亚低温CVD工艺，并且在达到时降低电介质的回流温度 电介质膜的期望的低k和间隙填充性能。 磷是用于吸收碱元素如钠的优选掺杂剂。 用于降低回流温度的附加掺杂剂包括但不限于硼，锗，砷，氟或其组合。

公开(公告)号：US20040266201A1

公开(公告)日：2004-12-30

申请号：US10604056

申请日：2003-06-24

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： William C. Wille ,  Daniel C. Edelstein ,  William J. Cote ,  Peter E. Biolsi ,  John E. Fritche ,  Allan W. Upham

IPC: H01L021/302 ,  H01L021/461

CPC classification number: H01L21/76808 ,  H01L21/31144 ,  H01L21/76804

Abstract: This invention relates to the manufacture of dual damascene interconnect structures in integrated circuit devices. Specifically, a method is disclosed for forming a single or dual damascene structure in a low-k dielectric thin film utilizing a planarizing material and a diffusion barrier material. In a preferred dual damascene embodiment of this method, the vias are formed first in the dielectric material, then the planarizing material is deposited in the vias and on the dielectric material, and the barrier material is deposited on the planarizing material. The trenches are then formed lithographically in the imaging material, etched through the barrier material into the planarizing material, and the trench pattern is transferred to the dielectric material. During and following the course of these etch steps, the imaging, barrier and planarizing materials are removed. The resultant dual damascene structure may then be metallized. With this method, the problem of photoresist poisoning by the interlevel dielectric material is alleviated.

Abstract translation: 本发明涉及集成电路器件中的双镶嵌互连结构的制造。 具体地，公开了一种利用平面化材料和扩散阻挡材料在低k电介质薄膜中形成单一或双镶嵌结构的方法。 在该方法的优选双镶嵌实施例中，首先在电介质材料中形成通孔，然后将平坦化材料沉积在通孔和介电材料上，并且阻挡材料沉积在平坦化材料上。 然后在成像材料中光刻地形成沟槽，通过阻挡材料蚀刻成平坦化材料，并将沟槽图案转移到电介质材料。 在这些蚀刻步骤的过程中和之后，去除成像，阻挡层和平坦化材料。 然后可以将所得的双镶嵌结构金属化。 通过这种方法，可以减轻层间电介质材料的光致抗蚀剂中毒问题。

公开(公告)号：US20030116439A1

公开(公告)日：2003-06-26

申请号：US10026176

申请日：2001-12-21

Applicant: International Business Machines Corporation

Inventor： Soon-Chen Seo ,  Carlos J. Sambucetti ,  Xiaomeng Chen ,  Zheng Chen ,  Vincent McGahay ,  Daniel C. Edelstein

IPC: C25D005/02 ,  H05K003/00 ,  C25D005/48

CPC classification number: H01L21/76852 ,  C23C18/1605 ,  C25D5/022 ,  C25D7/123 ,  H01L21/288 ,  H01L21/2885 ,  H01L21/76834 ,  H01L21/76873 ,  H01L21/76874 ,  H01L21/76885 ,  H05K3/4647

Abstract: An advanced back-end-of-line (BEOL) integration scheme for semiconductor devices using very low-k dielectric materials is disclosed. The disclosed method for forming a metal interconnect structure in a semiconductor integrated circuit device comprises forming the metal interconnects using a through-mask plating (TMP) process, and encapsulating the interconnects with a barrier layer by selectively depositing a barrier layer material using an electroless liner plating process or by non-selectively depositing a blanket insulator diffusion barrier layer using PVD or CVD techniques.

Abstract translation: 公开了使用非常低k电介质材料的半导体器件的先进的后端（BEOL）集成方案。 所公开的用于在半导体集成电路器件中形成金属互连结构的方法包括使用通孔掩模（TMP）工艺形成金属互连，并且通过使用无电镀衬底选择性地沉积阻挡层材料来封装互连件与阻挡层 电镀工艺或通过使用PVD或CVD技术非选择性地沉积覆盖绝缘体扩散阻挡层。

公开(公告)号：US20030068853A1

公开(公告)日：2003-04-10

申请号：US10299357

申请日：2002-11-18

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Richard A. Conti ,  Daniel C. Edelstein ,  Gill Yong Lee

IPC: H01L021/8238

CPC classification number: H01L21/02271 ,  C23C16/401 ,  H01L21/02112 ,  H01L21/02129 ,  H01L21/02205 ,  H01L21/02216 ,  H01L21/3122 ,  H01L21/31604 ,  H01L21/31625 ,  H01L21/31629 ,  H01L21/31633 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method is described for forming a low-k dielectric film, in particular, a pre-metal dielectric (PMD) on a semiconductor wafer which has good gap-filling characteristics. The method uses a thermal sub-atmospheric CVD process that includes a carbon-containing organometallic precusor such as TMCTS or OMCTS, an ozone-containing gas, and a source of dopants for gettering alkali elements and for lowering the reflow temperature of the dielectric while attaining the desired low-k and gap-filling properties of the dielectric film. Phosphorous is a preferred dopant for gettering alkali elements such as sodium. Additional dopants for lowering the reflow temperature include, but are not limited to boron, germanium, arsenic, fluorine or combinations thereof.

公开(公告)号：US20030017642A1

公开(公告)日：2003-01-23

申请号：US09910380

申请日：2001-07-20

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Richard A. Conti ,  Prakash Chimanlal Dev ,  David M. Dobuzinsky ,  Daniel C. Edelstein ,  Gill Y. Lee ,  Kia-Seng Low ,  Padraic C. Shafer ,  Alexander Simpson ,  Peter Wrschka

IPC: H01L035/24 ,  H01L051/00 ,  H01L051/40 ,  H01L023/58 ,  H01L021/302 ,  H01L021/461 ,  H01L021/31 ,  H01L021/469

CPC classification number: H01L21/28185 ,  H01L21/02126 ,  H01L21/02274 ,  H01L21/28194 ,  H01L21/31633 ,  H01L23/5329 ,  H01L23/53295 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A structure and method for an insulator layer having carbon-graded layers above a substrate is disclosed, wherein the concentration of carbon increases in each successive carbon-graded layer above the substrate. The insulator comprises a low-k dielectric having a dielectric constant less than 3.3. The carbon-graded layer increases adhesion between the substrate and the insulator and between the insulator and the conductor layer. The structure may also include stabilization interfaces between the carbon-graded layers. More specifically, the carbon-graded layers include a first layer adjacent the substrate having a carbon content between about 5% and 20%, a second layer above the first layer having a carbon content between about 10% and 30%, and a third layer above the second layer having a carbon content between about 20% and 40%.