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1.发明申请公开(公告)号：US20200042182A1
公开(公告)日：2020-02-06
申请号：US16597554
申请日：2019-10-09
发明人： Daniel G. Berger , Troy L. Graves-Abe , Subramanian S. Iyer , Toshiaki Kirihata , Arvind Kumar , Winfried W. Wilcke
摘要： A processor-memory system, a stacked-wafer processor-memory system, and a method of fabricating a processor-memory system are disclosed. In an embodiment, the invention provides a processor-memory system comprising a memory area, a multitude of specialized processors, and a management processor. The specialized processors are embedded in the memory area, and each of the specialized processors is configured for performing a specified set of operations using an associated memory domain in the memory area. The management processor is provided to control operations of an associated set of the specialized processors. In one embodiment, each of the specialized processors controls a respective one associated memory domain in the memory area. In an embodiment, the processor-memory system further comprises a specialized processor wafer. The specialized processor wafer includes the memory area, and the multitude of specialized processors are embedded in the specialized processor wafer.
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公开(公告)号：US09886193B2
公开(公告)日：2018-02-06
申请号：US14713689
申请日：2015-05-15
发明人： Daniel G. Berger , Troy L. Graves-Abe , Subramanian S. Iyer , Toshiaki Kirihata , Arvind Kumar , Winfried W. Wilcke
IPC分类号： G06F17/50 , G06F3/06 , H01L25/18 , H01L25/00 , H01L21/768
CPC分类号： G06F3/0604 , G06F3/0629 , G06F3/0673 , H01L21/76898 , H01L25/18 , H01L25/50 , H01L2224/16225 , H01L2225/06513 , H01L2225/06517 , H01L2225/06527 , H01L2225/06541 , H01L2225/06589
摘要： A processor-memory system, a stacked-wafer processor-memory system, and a method of fabricating a processor-memory system are disclosed. In an embodiment, the invention provides a processor-memory system comprising a memory area, a multitude of specialized processors, and a management processor. The specialized processors are embedded in the memory area, and each of the specialized processors is configured for performing a specified set of operations using an associated memory domain in the memory area. The management processor is provided to control operations of an associated set of the specialized processors. In one embodiment, each of the specialized processors controls a respective one associated memory domain in the memory area. In an embodiment, the processor-memory system further comprises a specialized processor wafer. The specialized processor wafer includes the memory area, and the multitude of specialized processors are embedded in the specialized processor wafer.
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公开(公告)号：US20140319694A1
公开(公告)日：2014-10-30
申请号：US13872371
申请日：2013-04-29
IPC分类号： H01L21/768 , H01L23/48
CPC分类号： H01L21/76898 , H01L2924/0002 , H01L2924/00
摘要： A method including implanting a region of a substrate with a dopant, and forming a through-substrate via in the substrate adjacent to a device, the through-substrate via passing through the region.
摘要翻译： 一种方法，包括用掺杂剂注入衬底的区域，以及在与器件相邻的衬底中形成穿通衬底通孔，所述通孔穿过所述区域。
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公开(公告)号：US10170337B2
公开(公告)日：2019-01-01
申请号：US14994598
申请日：2016-01-13
发明人： Christopher Collins , Mukta G. Farooq , Troy L. Graves-Abe , Brian J. Greene , Robert Hannon , Herbert L. Ho , Chandrasekharan Kothandaraman
IPC分类号： H01L21/322 , H01L21/768 , H01L21/308 , H01L29/167 , H01L23/522 , H01L23/528 , H01L23/532 , H01L21/265
摘要： A method of making a semiconductor device includes disposing a mask on a substrate; etching the mask to form an opening in the mask; etching a trench in the substrate beneath the opening in the mask; and implanting a dopant in an area of the substrate beneath the opening of the mask, the dopant capable of gettering mobile ions that can contaminate the substrate; wherein the dopant extends through the substrate from a sidewall of the trench and an endwall of the trench.
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公开(公告)号：US20150204932A1
公开(公告)日：2015-07-23
申请号：US14161309
申请日：2014-01-22
IPC分类号： G01R31/02 , G01R31/26 , H01L27/06 , H01L21/768 , H01L23/525
CPC分类号： G01R31/021 , G01M5/0033 , G01M5/0083 , G01R31/26 , H01L22/34 , H01L23/481 , H01L2924/0002 , H01L2924/00
摘要： A structure to detect changes in the integrity of vertical electrical connection structures including a semiconductor layer and an electrically conductive material extending through an entire depth of the semiconductor layer. The electrically conductive material has a geometry that encloses a pedestal portion of the semiconductor layer within an interior perimeter of the electrically conductive material. At least one semiconductor device is present on the pedestal portion of the semiconductor layer within the perimeter of the electrically conductive material.
摘要翻译： 检测包括半导体层和延伸穿过半导体层的整个深度的导电材料的垂直电连接结构的完整性变化的结构。 导电材料具有在导电材料的内部周边内包围半导体层的基座部分的几何形状。 至少一个半导体器件存在于导电材料的周边内的半导体层的基座部分上。
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公开(公告)号：US09060457B2
公开(公告)日：2015-06-16
申请号：US14043104
申请日：2013-10-01
IPC分类号： H05K3/42 , H01L23/48 , H01L23/532 , H01L21/768
CPC分类号： H05K3/423 , H01L21/76844 , H01L21/76846 , H01L21/76858 , H01L21/76898 , H01L23/481 , H01L23/53209 , H01L23/53214 , H01L23/53238 , H01L23/53242 , H01L23/53257 , H01L2924/0002 , Y10T428/12764 , H01L2924/00
摘要： A structure including a first intermetallic compound and an alloy layer parallel to a sidewall of an opening and separating a diffusion barrier from a conductive material, the diffusion barrier is in direct contact with the alloy layer, the alloy layer is in direct contact with the first intermetallic compound, the first intermetallic compound is in direct contact with the conductive material, the first intermetallic compound is a precipitate within a solid solution of an alloying material of the alloy layer and the conductive material, and is molecularly bound to both the alloy layer and the conductive material, the alloy layer excludes the conductive material, and a first high friction interface located between the diffusion barrier and the alloy layer extending in a direction parallel to the sidewall of the opening, the first high friction interface results in a mechanical bond between the diffusion barrier and the alloy layer.
摘要翻译： 一种包括第一金属间化合物和平行于开口侧壁的合金层并且与扩散阻挡层与导电材料分离的结构，所述扩散阻挡层与所述合金层直接接触，所述合金层与所述第一金属间化合物直接接触， 金属间化合物，第一金属间化合物与导电材料直接接触，第一金属间化合物是在合金层和导电材料的合金材料的固溶体内的沉淀物，并且分子结合到合金层和 所述导电材料，所述合金层排除所述导电材料，以及位于所述扩散阻挡层和所述合金层之间的第一高摩擦界面，所述第一高摩擦界面在平行于所述开口的侧壁的方向上延伸，所述第一高摩擦界面导致 扩散阻挡层和合金层。
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公开(公告)号：US09055703B2
公开(公告)日：2015-06-09
申请号：US14043127
申请日：2013-10-01
IPC分类号： H05K3/42 , H01L23/48 , H01L23/532 , H01L21/768
CPC分类号： H05K3/423 , H01L21/76844 , H01L21/76846 , H01L21/76858 , H01L21/76898 , H01L23/481 , H01L23/53209 , H01L23/53214 , H01L23/53238 , H01L23/53242 , H01L23/53257 , H01L2924/0002 , Y10T428/12764 , H01L2924/00
摘要： A structure including a seed layer located directly on top of and conformal to the diffusion barrier, wherein the seed layer is parallel to the sidewall and bottom of the opening, the seed layer comprises a crystalline structure suitable for plating copper; a first intermetallic compound and an alloy layer parallel to the sidewall of the opening and separating the seed layer from the conductive material, the first intermetallic compound is a precipitate within a solid solution of an alloying material of the alloy layer and the conductive material, and is molecularly bound to both the alloy layer and the conductive material, and a first high friction interface located between the seed layer and the alloy layer extending in a direction parallel to the sidewall of the opening, wherein the first high friction interface results in a mechanical bond between the seed layer and the alloy layer.
摘要翻译： 一种结构，其包括直接位于扩散阻挡层的顶部并与其形成共面的种子层，其中籽晶层平行于开口的侧壁和底部，晶种层包括适合镀铜的晶体结构; 第一金属间化合物和与开口的侧壁平行并且将种子层与导电材料分离的合金层，第一金属间化合物是在合金层和导电材料的合金材料的固溶体内的沉淀物，以及 与合金层和导电材料分子结合，以及位于种子层和合金层之间的第一高摩擦界面，其平行于开口的侧壁延伸，其中第一高摩擦界面导致机械 种子层和合金层之间的键合。
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8.发明授权Method of forming a through-silicon via utilizing a metal contact pad in a back-end-of-line wiring level to fill the through-silicon via 有权通过利用后端线路层中的金属接触焊盘形成贯通硅的方法，以填充穿硅通孔公开(公告)号：US08951906B2
公开(公告)日：2015-02-10
申请号：US14446634
申请日：2014-07-30
IPC分类号： H01L21/4763 , H01L21/768 , H01L21/306 , H01L23/00
CPC分类号： H01L21/76898 , H01L21/2885 , H01L21/306 , H01L21/6835 , H01L21/76841 , H01L21/76846 , H01L21/76879 , H01L23/562 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/13 , H01L2221/1084 , H01L2221/68372 , H01L2221/68381 , H01L2224/0401 , H01L2224/05022 , H01L2224/05572 , H01L2224/05647 , H01L2224/05666 , H01L2224/13023 , H01L2224/131 , H01L2924/00014 , H01L2924/07802 , H01L2924/00012 , H01L2924/01074 , H01L2924/014 , H01L2924/00 , H01L2224/05552
摘要： A method for fabricating through-silicon vias (TSVs) for semiconductor devices is provided. Specifically, the method involves utilizing copper contact pads in a back-end-of-line wiring level, wherein the copper contact pads act as cathodes for performing an electroplating technique to fill TSVs with plated-conductive material (e.g., copper) from an electroplating solution. Moreover, the method provides a way to fill high aspect ratio TSVs with minimal additional semiconductor fabrication process steps, which can increase the silicon area that is available for forming additional electronic components on integrated circuits.
摘要翻译： 提供了一种用于制造用于半导体器件的硅通孔（TSV）的方法。 具体地，该方法包括在后端线路布线层中利用铜接触焊盘，其中铜接触焊盘用作执行电镀技术的阴极，用电镀导电材料（例如铜）填充TSV 解。 此外，该方法提供了通过最小的附加半导体制造工艺步骤填充高纵横比TSV的方法，其可以增加可用于在集成电路上形成附加电子部件的硅面积。
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9.发明授权Method of forming a through-silicon via utilizing a metal contact pad in a back-end-of-line wiring level to fill the through-silicon via 有权通过利用后端线路层中的金属接触焊盘形成贯通硅的方法，以填充穿硅通孔公开(公告)号：US08889542B2
公开(公告)日：2014-11-18
申请号：US14255067
申请日：2014-04-17
IPC分类号： H01L21/4763 , H01L21/768
CPC分类号： H01L21/76898 , H01L21/2885 , H01L21/306 , H01L21/6835 , H01L21/76841 , H01L21/76846 , H01L21/76879 , H01L23/562 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/13 , H01L2221/1084 , H01L2221/68372 , H01L2221/68381 , H01L2224/0401 , H01L2224/05022 , H01L2224/05572 , H01L2224/05647 , H01L2224/05666 , H01L2224/13023 , H01L2224/131 , H01L2924/00014 , H01L2924/07802 , H01L2924/00012 , H01L2924/01074 , H01L2924/014 , H01L2924/00 , H01L2224/05552
摘要： A method for fabricating through-silicon vias (TSVs) for semiconductor devices is provided. Specifically, the method involves utilizing copper contact pads in a back-end-of-line wiring level, wherein the copper contact pads act as cathodes for performing an electroplating technique to fill TSVs with plated-conductive material (e.g., copper) from an electroplating solution. Moreover, the method provides a way to fill high aspect ratio TSVs with minimal additional semiconductor fabrication process steps, which can increase the silicon area that is available for forming additional electronic components on integrated circuits.
摘要翻译： 提供了一种用于制造用于半导体器件的硅通孔（TSV）的方法。 具体地，该方法包括在后端线路布线层中利用铜接触焊盘，其中铜接触焊盘用作执行电镀技术的阴极，用电镀导电材料（例如铜）填充TSV 解。 此外，该方法提供了通过最小的附加半导体制造工艺步骤填充高纵横比TSV的方法，其可以增加可用于在集成电路上形成附加电子部件的硅面积。
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公开(公告)号：US20140264756A1
公开(公告)日：2014-09-18
申请号：US13826628
申请日：2013-03-14
发明人： Christopher N. Collins , Mukta G. Farooq , Troy L. Graves-Abe , Joyce C. Liu , Gerd Pfeiffer , Thuy L. Tran-Quinn
IPC分类号： H01L29/32 , H01L23/538
CPC分类号： H01L25/0657 , H01L21/76898 , H01L23/5384 , H01L29/32 , H01L2224/16225 , H01L2225/06541 , H01L2924/0002 , H01L2924/15311 , H01L2924/00
摘要： The formation of TSVs (through substrate vias) for 3D applications has proven to be defect dependent upon the type of starting semiconductor substrate employed. In addition to the initial formation of TSVs via Bosch processing, backside 3D wafer processing has also shown a defect dependency on substrate type. High yield of TSV formation can be achieved by utilizing a substrate that embodies bulk micro defects (BMD) at a density between 1e4/cc (particles per cubic centimeter) and 1e7/cc and having equivalent diameter less than 55 nm (nanometers).
摘要翻译： 已经证明用于3D应用的TSV（通过衬底通孔）的形成缺陷取决于所采用的起始半导体衬底的类型。 除了通过博世处理初始形成TSV之外，背面3D晶片处理也显示了对衬底类型的缺陷依赖性。 通过利用以1e4 / cc（每立方厘米颗粒）和1e7 / cc之间的密度并且具有小于55nm（纳米）的等效直径的体积微观缺陷（BMD）来实现高产率的TSV形成。
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