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公开(公告)号：US06967072B2
公开(公告)日：2005-11-22
申请号：US09921938
申请日：2001-08-02
IPC分类号： B01J19/08 , C23C16/26 , C23C16/46 , G03C5/00 , G03F7/075 , G03F7/09 , H01L21/027 , H01L21/283 , H01L21/311 , H01L21/312 , H01L21/314 , H01L21/316 , H01L21/3205 , H01L21/768 , G03F7/004 , G03F7/085
CPC分类号： H01L21/31144 , G03F7/0757 , G03F7/091 , H01L21/0276 , H01L21/76802 , H01L21/76825 , H01L21/76832
摘要： A method for forming a patterned amorphous carbon layer in a semiconductor stack, including forming an amorphous carbon layer on a substrate and forming a silicon containing photoresist layer on top of the amorphous carbon layer. Thereafter, the method includes developing a pattern transferred into the resist layer with a photolithographic process and etching through the amorphous carbon layer in at least one region defined by the pattern in the resist layer, wherein a resist layer hard mask is formed in an outer portion of the photoresist layer during etching.
摘要翻译： 一种在半导体堆叠中形成图案化的非晶碳层的方法，包括在基底上形成无定形碳层，并在无定形碳层的顶部形成含硅光致抗蚀剂层。 此后，该方法包括通过光刻工艺显影转印到抗蚀剂层中的图案，并且在由抗蚀剂层中的图案限定的至少一个区域中通过无定形碳层进行蚀刻，其中在外部形成抗蚀剂层硬掩模 的光刻胶层。
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公开(公告)号：US07332262B2
公开(公告)日：2008-02-19
申请号：US11154741
申请日：2005-06-16
CPC分类号： H01L21/31144 , G03F7/0757 , G03F7/091 , H01L21/0276 , H01L21/76802 , H01L21/76825 , H01L21/76832
摘要： A method for forming a patterned amorphous carbon layer in a semiconductor stack, including forming an amorphous carbon layer on a substrate and forming a silicon containing photoresist layer on top of the amorphous carbon layer. Thereafter, the method includes developing a pattern transferred into the resist layer with a photolithographic process and etching through the amorphous carbon layer in at least one region defined by the pattern in the resist layer, wherein a resist layer hard mask is formed in an outer portion of the photoresist layer during etching.
摘要翻译： 一种在半导体堆叠中形成图案化的非晶碳层的方法，包括在基底上形成无定形碳层，并在无定形碳层的顶部形成含硅光致抗蚀剂层。 此后，该方法包括通过光刻工艺显影转印到抗蚀剂层中的图案，并且在由抗蚀剂层中的图案限定的至少一个区域中通过无定形碳层进行蚀刻，其中在外部形成抗蚀剂层硬掩模 的光刻胶层。
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3.发明授权Low temperature process for depositing a high extinction coefficient non-peeling optical absorber for a scanning laser surface anneal of implanted dopants 有权用于沉积用于注入掺杂剂的扫描激光表面退火的高消光系数非剥离光吸收剂的低温工艺公开(公告)号：US07968473B2
公开(公告)日：2011-06-28
申请号：US11697267
申请日：2007-04-05
IPC分类号： H01L21/00
CPC分类号： H01L21/02115 , C23C14/02 , C23C14/0605 , C23C14/35 , H01L21/02266 , H01L21/02354 , H01L21/2236 , H01L21/26513 , H01L21/268 , H01L21/3146
摘要： A plasma enhanced physical vapor deposition process deposits an amorphous carbon layer on an ion-implanted wafer for use in dynamic surface annealing of the wafer with an intense line beam of a laser wavelength. The deposition process is carried out at a wafer temperature below the dopant clustering threshold temperature, and includes introducing the wafer into a chamber having a carbon-containing target overlying the wafer, and furnishing a carrier gas into the chamber. The process further includes generating a wafer bias voltage and applying target source power to the carbon-containing target sufficient to produce ion bombardment of the carbon-containing target. The wafer bias voltage is set to a level at which the amorphous carbon layer that is deposited has a desired extinction coefficient at the laser wavelength.
摘要翻译： 等离子体增强的物理气相沉积工艺在离子注入晶片上沉积无定形碳层，用于具有激光波长的强线束的晶片的动态表面退火。 沉积工艺在低于掺杂剂聚集阈值温度的晶片温度下进行，并且包括将晶片引入到具有覆盖晶片的含碳靶的腔室中，并将载气提供到腔室中。 该方法还包括产生晶片偏置电压并将目标源功率施加到含碳靶足以产生含碳靶的离子轰击。 将晶片偏置电压设定为在激光波长处具有期望的消光系数的被沉积的无定形碳层的水平。
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4.发明授权Method of reducing critical dimension bias during fabrication of a semiconductor device 有权在半导体器件制造期间减小临界尺寸偏压的方法公开(公告)号：US07737040B2
公开(公告)日：2010-06-15
申请号：US11983450
申请日：2007-11-09
申请人： Christopher Dennis Bencher , Melvin Warren Montgomery , Alexander Buxbaum , Yung-Hee Yvette Lee , Jian Ding , Gilad Almogy , Wendy H. Yeh
发明人： Christopher Dennis Bencher , Melvin Warren Montgomery , Alexander Buxbaum , Yung-Hee Yvette Lee , Jian Ding , Gilad Almogy , Wendy H. Yeh
IPC分类号： H01L21/00 , H01L21/311
摘要： An anti-reflective hard mask layer left on a radiation-blocking layer during fabrication of a reticle provides functionality when the reticle is used in a semiconductor device manufacturing process.
摘要翻译： 当在半导体器件制造工艺中使用掩模版时，在掩模版的制造期间留在辐射阻挡层上的抗反射硬掩模层提供了功能。
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公开(公告)号：US20080070421A1
公开(公告)日：2008-03-20
申请号：US11533505
申请日：2006-09-20
IPC分类号： H01L21/469
CPC分类号： H01L21/76829 , C23C16/30 , C23C16/45523 , H01L21/02126 , H01L21/022 , H01L21/02216 , H01L21/02274 , H01L21/0234 , H01L21/02348 , H01L21/02351 , H01L21/02362 , H01L21/3122 , H01L21/31633 , H01L21/76835
摘要： A method is provided for processing a substrate surface by delivering a first gas mixture comprising a first organosilicon compound, a first oxidizing gas, and one or more hydrocarbon compounds into a chamber at deposition conditions sufficient to deposit a first low dielectric constant film on the substrate surface. A second gas mixture having a second organosilicon compound and a second oxidizing gas is delivered into the chamber at deposition conditions sufficient to deposit a second low dielectric constant film on the first low dielectric constant film. The flow rate of the second oxidizing gas into the chamber is increased, and the flow rate of the second organosilicon compound into the chamber is decreased to deposit an oxide rich cap on the second low dielectric constant film.
摘要翻译： 提供了一种通过将包含第一有机硅化合物，第一氧化气体和一种或多种烃化合物的第一气体混合物输送到室中的方法来处理衬底表面，该沉积条件足以在衬底上沉积第一低介电常数膜 表面。 具有第二有机硅化合物和第二氧化气体的第二气体混合物在足以在第一低介电常数膜上沉积第二低介电常数膜的沉积条件下被输送到室中。 进入室内的第二氧化气体的流量增加，第二有机硅化合物进入室的流量减少，从而在第二低介电常数膜上沉积氧化物富集盖。
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公开(公告)号：US07148156B2
公开(公告)日：2006-12-12
申请号：US11053193
申请日：2005-02-08
IPC分类号： H01L21/31 , H01L21/469
CPC分类号： H01L21/76826 , H01L21/02115 , H01L21/02126 , H01L21/022 , H01L21/02216 , H01L21/02274 , H01L21/02304 , H01L21/0234 , H01L21/3105 , H01L21/31122 , H01L21/31144 , H01L21/3146 , H01L21/31633 , H01L21/3212 , H01L21/7681 , H01L21/76828 , H01L21/76829 , H01L21/7684
摘要： A method is provided for processing a substrate including removing amorphous carbon material disposed on a low k dielectric material with minimal or reduced defect formation and minimal dielectric constant change of the low k dielectric material. In one aspect, the invention provides a method for processing a substrate including depositing at least one dielectric layer on a substrate surface, wherein the dielectric layer comprises silicon, oxygen, and carbon and has a dielectric constant of about 3 or less, forming amorphous carbon material on the at least one dielectric layer, and removing the one or more amorphous carbon layers by exposing the one or more amorphous carbon layers to a plasma of a hydrogen-containing gas.
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7.发明授权Method and apparatus for reducing copper oxidation and contamination in a semiconductor device 有权减少半导体器件中的铜氧化和污染的方法和装置公开(公告)号：US06355571B1
公开(公告)日：2002-03-12
申请号：US09365129
申请日：1999-07-30
IPC分类号： H01L21302
CPC分类号： H01L21/76834 , B08B7/0035 , C23C16/0245 , C23G5/00 , H01L21/02063 , H01L21/02068 , H01L21/02071 , H01L21/02074 , H01L21/31116 , H01L21/3148 , H01L21/3185 , H01L21/32136 , H01L21/76807 , H01L21/76877 , H01L21/76883 , H01L23/53238 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： A method and apparatus for reducing oxidation of an interface of a semiconductor device thereby improving adhesion of subsequently formed layers and/or devices is disclosed. The semiconductor device has at least a first layer and a second layer wherein the interface is disposed between said first and second layers. The method includes the steps of providing the first layer having a partially oxidized interface; introducing a hydrogen-containing plasma to the interface; reducing the oxidized interface and introducing second-layer-forming compounds to the hydrogen-containing plasma. A concomitant apparatus (i.e., a semiconductor device interface) has a first insulating layer, one or more conductive devices disposed within the insulating layer, the insulating layer and conductive devices defining the interface, wherein the interface is treated with a continuous plasma treatment to remove oxidation and deposit a second layer thereupon. The insulating layer of the interface is selected from oxides and nitrides and is preferably a nitride.
摘要翻译： 公开了一种用于减少半导体器件的界面的氧化从而改善随后形成的层和/或器件的粘合性的方法和装置。 半导体器件具有至少第一层和第二层，其中界面设置在所述第一层和第二层之间。 该方法包括提供具有部分氧化界面的第一层的步骤; 向界面引入含氢等离子体; 还原氧化界面并将第二层形成化合物引入到含氢等离子体中。 伴随的装置（即，半导体器件接口）具有第一绝缘层，设置在绝缘层内的一个或多个导电器件，绝缘层和限定界面的导电器件，其中界面用连续等离子体处理来去除 氧化并沉积第二层。 界面的绝缘层选自氧化物和氮化物，优选为氮化物。
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8.发明授权Low temperature process for depositing a high extinction coefficient non-peeling optical absorber for a scanning laser surface anneal of implanted dopants 失效用于沉积用于注入掺杂剂的扫描激光表面退火的高消光系数非剥离光吸收剂的低温工艺公开(公告)号：US08338316B2
公开(公告)日：2012-12-25
申请号：US13111306
申请日：2011-05-19
IPC分类号： H01L21/00
CPC分类号： H01L21/02115 , C23C14/02 , C23C14/0605 , C23C14/35 , H01L21/02266 , H01L21/02354 , H01L21/2236 , H01L21/26513 , H01L21/268 , H01L21/3146
摘要： A plasma enhanced physical vapor deposition process deposits an amorphous carbon layer on an ion-implanted wafer for use in dynamic surface annealing of the wafer with an intense line beam of a laser wavelength. The deposition process is carried out at a wafer temperature below the dopant clustering threshold temperature, and includes introducing the wafer into a chamber having a carbon-containing target overlying the wafer, and furnishing a carrier gas into the chamber. The process further includes generating a wafer bias voltage and applying target source power to the carbon-containing target sufficient to produce ion bombardment of the carbon-containing target. The wafer bias voltage is set to a level at which the amorphous carbon layer that is deposited has a desired extinction coefficient at the laser wavelength.
摘要翻译： 等离子体增强的物理气相沉积工艺在离子注入晶片上沉积无定形碳层，用于具有激光波长的强线束的晶片的动态表面退火。 沉积工艺在低于掺杂剂聚集阈值温度的晶片温度下进行，并且包括将晶片引入到具有覆盖晶片的含碳靶的腔室中，并将载气提供到腔室中。 该方法还包括产生晶片偏置电压并将目标源功率施加到含碳靶足以产生含碳靶的离子轰击。 将晶片偏置电压设定为在激光波长处具有期望的消光系数的被沉积的无定形碳层的水平。
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9.发明申请公开(公告)号：US20100136792A1
公开(公告)日：2010-06-03
申请号：US12603371
申请日：2009-10-21
CPC分类号： H01L21/0337
摘要： Embodiments of the present invention pertain to methods of forming patterned features on a substrate having a reduced pitch in two dimensions as compared to what is possible using standard photolithography processing techniques using a single high-resolution photomask. A spacer layer is formed over a two-dimensional square grid of cores with a thickness chosen to leave a dimple at the center of four cores on the corners of a square. The spacer layer is etched back to reveal the substrate at the centers of the square. Removing the core material results in double the pattern density of the lithographically defined grid of cores. The regions of exposed substrate may be filled again with core material and the process repeated to quadruple the pattern density.
摘要翻译： 本发明的实施例涉及在使用单个高分辨率光掩模的标准光刻处理技术的可能性方面，在具有减小的间距的基板上形成图案化特征的方法。 间隔层形成在芯的二维正方形网格上，其厚度被选择为在正方形的角上的四个芯的中心处留下凹坑。 将间隔层回蚀刻以在正方形的中心露出基底。 去除核心材料会导致光刻图形格网格的图案密度增加一倍。 暴露的衬底的区域可以再次用芯材料填充，并且重复该过程以使图案密度增加四倍。
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公开(公告)号：US20100022100A1
公开(公告)日：2010-01-28
申请号：US12573794
申请日：2009-10-05
IPC分类号： H01L21/31
CPC分类号： H01L21/76829 , C23C16/30 , C23C16/45523 , H01L21/02126 , H01L21/022 , H01L21/02216 , H01L21/02274 , H01L21/0234 , H01L21/02348 , H01L21/02351 , H01L21/02362 , H01L21/3122 , H01L21/31633 , H01L21/76835
摘要： A method is provided for processing a substrate surface by delivering a first gas mixture comprising a first organosilicon compound, a first oxidizing gas, and one or more hydrocarbon compounds into a chamber at deposition conditions sufficient to deposit a first low dielectric constant film on the substrate surface. A second gas mixture having a second organosilicon compound and a second oxidizing gas is delivered into the chamber at deposition conditions sufficient to deposit a second low dielectric constant film on the first low dielectric constant film. The flow rate of the second oxidizing gas into the chamber is increased, and the flow rate of the second organosilicon compound into the chamber is decreased to deposit an oxide rich cap on the second low dielectric constant film.
摘要翻译： 提供了一种通过将包含第一有机硅化合物，第一氧化气体和一种或多种烃化合物的第一气体混合物输送到室中的方法来处理衬底表面，该沉积条件足以在衬底上沉积第一低介电常数膜 表面。 具有第二有机硅化合物和第二氧化气体的第二气体混合物在足以在第一低介电常数膜上沉积第二低介电常数膜的沉积条件下被输送到室中。 进入室内的第二氧化气体的流量增加，第二有机硅化合物进入室的流量减少，从而在第二低介电常数膜上沉积氧化物富集盖。
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