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1.发明授权公开(公告)号：US06553443B1
公开(公告)日：2003-04-22
申请号：US09406936
申请日：1999-09-28
IPC分类号： G06F1326
CPC分类号： H04Q3/54591 , H04Q2213/13053 , H04Q2213/13058 , H04Q2213/1309 , H04Q2213/13092 , H04Q2213/131 , H04Q2213/13103 , H04Q2213/13106 , H04Q2213/13109 , H04Q2213/1316 , H04Q2213/13162 , H04Q2213/13178 , H04Q2213/13292 , H04Q2213/1332
摘要： A communications system includes a communications channel, a first processing unit; and interface unit, and an interrupt controller. The first processing unit is adapted to monitor the communications channel and provide a plurality of status bits. The interface unit includes an interrupt register. The interrupt controller is adapted to identify a plurality of interrupts in response to changes in the status bits. Each interrupt has a priority, and the interrupt controller is adapted to store selected interrupts in the interrupt register in an order determined by the priority of the interrupts. A method includes monitoring a communications channel. A plurality of status bits associated with the monitoring are provided. A plurality of interrupts are identified based on changes in the status bits, each interrupt having a priority. Selected interrupts are stored in an interrupt queue in an order determined by the priority of the interrupts.
摘要翻译： 通信系统包括通信信道，第一处理单元， 接口单元和中断控制器。 第一处理单元适于监视通信信道并提供多个状态位。 接口单元包括一个中断寄存器。 中断控制器适于响应于状态位的变化来识别多个中断。 每个中断具有优先权，并且中断控制器适合于按照中断优先级确定的顺序将所选中断存储在中断寄存器中。 一种方法包括监视通信信道。 提供与监视相关联的多个状态位。 基于状态位的变化来识别多个中断，每个中断具有优先权。 所选择的中断按照中断优先级确定的顺序存储在中断队列中。
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公开(公告)号：US07265640B1
公开(公告)日：2007-09-04
申请号：US11021868
申请日：2004-12-23
申请人： Michael A. Nix
发明人： Michael A. Nix
CPC分类号： H03F3/45766 , H03F3/45183 , H03F3/45188 , H03F2203/45081 , H03F2203/45188 , H03F2203/45681
摘要： An example embodiment is directed to shifting the common mode voltage of an analog oscillation stage toward a center line between the upper and lower power-supply rails of a first digital circuit. The first digital circuit has a digital input port adapted to respond to signal transitions defined between the supply rails, and the analog oscillation stage generates an oscillating analog signal that has a common-mode voltage that is not centered between the upper and lower power-supply rails. The oscillating analog signal, which drives the digital input port, changes alternately with the phases of the oscillating analog signal. To shift the common mode voltage of an analog oscillation stage toward the center line between the rails, a feedback circuit generates a contending digital signal that drives the digital input port with alternating states as defined by opposite phases.
摘要翻译： 示例性实施例涉及将模拟振荡级的共模电压朝向第一数字电路的上电源轨和下电源轨之间的中心线移动。 第一数字电路具有适于响应于在电源轨之间定义的信号转换的数字输入端口，并且模拟振荡级产生振荡模拟信号，该振荡模拟信号具有不在上下电源之间的共模电压 轨道 驱动数字输入端口的振荡模拟信号与振荡模拟信号的相位交替变化。 为了将模拟振荡级的共模电压转移到轨道之间的中心线，反馈电路产生竞争数字信号，该数字信号以相反相定义的交替状态驱动数字输入端口。
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公开(公告)号：US07106099B1
公开(公告)日：2006-09-12
申请号：US10970969
申请日：2004-10-22
申请人： Michael A. Nix
发明人： Michael A. Nix
IPC分类号： G06F7/38 , H03K19/177 , H03K5/159 , H03H7/30 , H03H7/40
CPC分类号： H04L25/03063
摘要： A decision feedback equalization (“DFE”) technique is suitable for use in a serializer-deserializer (“SERDES”) receiver in an integrated circuit (IC). The IC has a summing node coupled to a return-to-zero (“RTZ”) data latch register. The RTZ data latch register has a first (“even”) series of RTZ data latches and a second (“odd”) series of RTZ data latches. A first even tap is coupled to the first even RTZ data latch and provides a feedback signal to the summing node on a first portion of a local clock cycle. A first odd tap is coupled to the first odd RTZ data latch and provides an odd feedback signal to the summing node on a second portion of the local clock cycle.
摘要翻译： 决策反馈均衡（“DFE”）技术适用于集成电路（IC）中的串行器 - 解串器（“SERDES”）接收器。 IC具有耦合到归零（“RTZ”）数据锁存寄存器的求和节点。 RTZ数据锁存寄存器具有第一（“偶数”）系列RTZ数据锁存器和第二（“奇数”）系列RTZ数据锁存器。 第一偶数抽头耦合到第一偶数RTZ数据锁存器，并且在本地时钟周期的第一部分上向求和节点提供反馈信号。 第一奇数抽头耦合到第一奇数RTZ数据锁存器，并且在本地时钟周期的第二部分上向求和节点提供奇数反馈信号。
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公开(公告)号：US07012985B1
公开(公告)日：2006-03-14
申请号：US10909800
申请日：2004-07-30
申请人： Michael A. Nix
发明人： Michael A. Nix
IPC分类号： H03K21/00
CPC分类号： H03K23/42
摘要： A frequency-divider circuit performs a division operation using a divisor that can include a fraction. In one such embodiment, a first divider module includes a divider circuit that operates to divide the frequency of an input clock signal and a phase-quadrature circuit. The first divider module generates a first-divider-output signal having periodic signals with regular phase displacement therebetween and a common period that is an integer multiple of the clock signal. Using this first-divider-output signal, a second divider module performs another divide operation and is clocked as a function of a delay effected by at least one of the periodic signals. The present invention is useful in a wide variety of applications including applications having a high frequency clock source that cannot tolerate excessive loading or jitter attributable to a divider circuit.
摘要翻译： 分频器电路使用可以包括分数的除数来执行除法运算。 在一个这样的实施例中，第一分频器模块包括分频器电路，其操作以分频输入时钟信号和相位正交电路的频率。 第一分频器模块产生具有周期性信号的第一分频器输出信号，其中它们之间具有规则的相位位移，并且具有作为时钟信号的整数倍的公共周期。 使用该第一分频器输出信号，第二分频器模块执行另一个除法运算，并且作为由至少一个周期信号影响的延迟的函数进行计时。 本发明在各种各样的应用中是有用的，包括具有不能容忍归因于分频器电路的过载或抖动的高频时钟源的应用。
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公开(公告)号：US5420815A
公开(公告)日：1995-05-30
申请号：US783837
申请日：1991-10-29
申请人： Michael A. Nix , John Bartkowiak
发明人： Michael A. Nix , John Bartkowiak
CPC分类号： G06F7/57 , G06F7/5443 , G06F2207/3884 , G06F7/483
摘要： A multiplication system performs a series of multiplications and accumulations of plural pairs of first and second operands. The system includes first and second buses, a memory for storing the plural pairs of first and second operands, and a read buffer coupled to the memory for sequentially reading the first and second operands. An accumulator coupled to the first bus receives the first operands from the read buffer and stores the first operands. A multiplier, coupled to the first and second buses, receives the first and second operands in parallel over the first and second buses respectively from the accumulator and the read buffer respectively to provide a series of products. The system further includes an accumulator for accumulating the products to provide a final accumulated product.
摘要翻译： 乘法系统执行多对第一和第二操作数的一系列乘法和累加。 该系统包括第一和第二总线，用于存储多对第一和第二操作数的存储器，以及耦合到存储器以用于顺序读取第一和第二操作数的读缓冲器。 耦合到第一总线的累加器从读缓冲器接收第一操作数并存储第一操作数。 耦合到第一和第二总线的乘法器分别从累加器和读取缓冲器分别在第一和第二总线上并行地接收第一和第二操作数，以提供一系列产品。 该系统还包括用于累积产品以提供最终累积产品的蓄能器。
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公开(公告)号：US5347480A
公开(公告)日：1994-09-13
申请号：US53959
申请日：1993-04-27
CPC分类号： G06F17/10 , G06F7/5443 , G06F9/30014 , G06F9/30167 , G06F9/30181
摘要： An apparatus for processing a received signal according to a digital signal processing algorithm having a multiplier and a limit and quantization circuit appropriately connected within the apparatus to permit operation of the multiplier and the limit and quantization circuit in parallel with logic processing by the apparatus. The address bus system of the apparatus is connected to the parallel-connected components and conveys instructions to the parallel-connected components, at least in part, by predetermined address information via the address bus system.
摘要翻译： 一种用于根据数字信号处理算法处理接收信号的装置，该数字信号处理算法具有在装置内适当连接的乘法器和限制量化电路，以允许乘法器和极限量化电路与该装置的逻辑处理并行进行操作。 该设备的地址总线系统连接到并联连接的组件，并且至少部分地通过地址总线系统通过预定的地址信息将指令传送到并联连接的组件。
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公开(公告)号：US4926363A
公开(公告)日：1990-05-15
申请号：US251309
申请日：1988-09-30
申请人： Michael A. Nix
发明人： Michael A. Nix
IPC分类号： G01R31/26 , G01R31/28 , G01R31/317 , G06F11/22 , G06F11/273 , H01L21/822 , H01L27/04 , H04M3/24 , H04Q11/04
CPC分类号： G06F11/2733 , G06F11/2736 , H04M3/244 , H04Q11/0414
摘要： A modular test structure for performing testing on a single chip having a plurality of different functional blocks is provided which includes test interface logic circuitry (24) formed on each of the functional blocks (16-22) so that each block can be operated as a self-contained module. Test generation logic circuitry (40) is formed in a bus interface unit (12) and is used to select one or more of the functional blocks (16-22) for testing and for placing the selected functional blocks (16-22) in a test mode. The test interface logic circuitry (24) on the selected functional blocks under test sends data direction information to the bus interface unit (12) to indicate how individual bits of a data bus are to be used for inputs and outputs during testing.
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公开(公告)号：US08410833B2
公开(公告)日：2013-04-02
申请号：US13076071
申请日：2011-03-30
IPC分类号： H03L7/00
CPC分类号： G06F1/24 , H03K17/223
摘要： A power-up control circuit utilizes on-chip circuits, multiple voltages, a ring oscillator and counter, and edge and level detection circuits to guarantee reset during power-up conditions and continues the reset state with a variable length counter to guarantee a predictable reset. In addition, a clean start-up after a logical power-down condition is provided.
摘要翻译： 上电控制电路利用片上电路，多电压，环形振荡器和计数器以及边沿和电平检测电路来保证在上电条件下的复位，并用可变长度计数器继续复位状态，以保证可预测的复位 。 另外，在逻辑掉电状态之后提供干净的启动。
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公开(公告)号：US07091773B1
公开(公告)日：2006-08-15
申请号：US10900945
申请日：2004-07-28
申请人： Brian T. Brunn , Michael A. Nix
发明人： Brian T. Brunn , Michael A. Nix
IPC分类号： H03F1/36
CPC分类号： H03G11/02 , H03F1/34 , H03F3/45183 , H03F3/45475 , H03F2203/45472 , H03F2203/45652 , H03G11/008
摘要： A limiting circuit includes an input transconductance stage, an output transconductance stage, a feedback transconductance stage, first and second resistive loads, and a level limiting circuit. The input transconductance stage is operably coupled to convert an input voltage signal into an input current signal. The first resistive load is operably coupled to convert the input current signal and a feedback current signal into an intermediate output voltage signal. The output transconductance stage is operably coupled to convert the intermediate output voltage signal into an output current signal. The second resistive load is operably coupled to convert the output current signal into an output voltage signal. The feedback transconductance stage is operably coupled to produce the feedback current signal based on the output voltage signal. The level limiting module is operably coupled to limit at least one voltage level of the feedback transconductance stage.
摘要翻译： 限制电路包括输入跨导级，输出跨导级，反馈跨导级，第一和第二阻性负载以及电平限制电路。 输入跨导级可操作地耦合以将输入电压信号转换成输入电流信号。 第一电阻负载可操作地耦合以将输入电流信号和反馈电流信号转换成中间输出电压信号。 输出跨导级可操作地耦合以将中间输出电压信号转换成输出电流信号。 第二电阻负载可操作地耦合以将输出电流信号转换成输出电压信号。 反馈跨导级可操作地耦合以产生基于输出电压信号的反馈电流信号。 电平限制模块可操作地耦合以限制反馈跨导级的至少一个电压电平。
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10.发明授权公开(公告)号：US07058120B1
公开(公告)日：2006-06-06
申请号：US10051222
申请日：2002-01-18
申请人： Jinghui Lu , Shahriar Rokhsaz , Stephen D. Anderson , Michael A. Nix , Ahmed Younis , Michael Ren Kent , Yvette P. Lee , Firas N. Abughazaleh , Brian T. Brunn , Moises E. Robinson , Kazi S. Hossain
发明人： Jinghui Lu , Shahriar Rokhsaz , Stephen D. Anderson , Michael A. Nix , Ahmed Younis , Michael Ren Kent , Yvette P. Lee , Firas N. Abughazaleh , Brian T. Brunn , Moises E. Robinson , Kazi S. Hossain
CPC分类号： H03L7/093 , H03K5/1565 , H03M9/00 , H04L7/0004 , H04L7/033 , H04W4/18
摘要： A transceiver includes a receiver section and a transmitter section. The receiver section includes a clocking circuit, a serial-to-parallel module, and compensation. The transmitter section includes a clocking circuit, parallel-to-serial module, and compensation. The compensation within the receiver section and transmitter section compensates for integrated circuit (IC) processing limits and/or integrated circuit (IC) fabrication limits within the clocking circuits, serial-to-parallel module, and parallel-to-serial module that would otherwise limit the speed at which the transceiver could transport data.
摘要翻译： 收发机包括接收机部分和发射机部分。 接收器部分包括时钟电路，串行到并行模块和补偿。 发射机部分包括时钟电路，并行到串行模块和补偿。 接收器部分和发射器部分内的补偿补偿了时钟控制电路，串行到并行模块和并行到串行模块的集成电路（IC）处理限制和/或集成电路（IC）制造限制，否则 限制收发器可以传输数据的速度。
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