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    Multiple level cell phase-change memory devices having pre-reading operation resistance drift recovery, memory systems employing such devices and methods of reading memory devices
    3.
    发明授权
    Multiple level cell phase-change memory devices having pre-reading operation resistance drift recovery, memory systems employing such devices and methods of reading memory devices 有权
    具有预读操作电阻漂移恢复的多电平单元相变存储器件，采用这种器件的存储器系统以及读取存储器件的方法

    公开(公告)号：US08199567B2

    公开(公告)日：2012-06-12

    申请号：US13084906

    申请日：2011-04-12

    申请人： Jeong Chang-Wook ,  Gi-Tae Jeong ,  Hyeong-Jun Kim ,  Seung-Pil Ko

    发明人： Jeong Chang-Wook ,  Gi-Tae Jeong ,  Hyeong-Jun Kim ,  Seung-Pil Ko

    IPC分类号： G11C11/00

    CPC分类号： G11C11/56 ,  G11C11/5678 ,  G11C13/0004 ,  G11C13/004 ,  G11C13/0069 ,  G11C2013/0078 ,  Y10S977/754

    摘要： A memory device comprises a plurality of memory cells, each memory cell comprising a memory cell material that has an initial resistance that is determined in response to an applied programming current in a programming operation, the resistance of the memory cell varying from the initial resistance over a time period following the programming operation, and each memory cell being connected to a conduction line of the memory device that is used to apply the programming current to program the resistance of the corresponding memory cell in the programming operation and that is used to apply a read current to read the resistance of the corresponding memory cell in a read operation. A modification circuit modifies the resistance of a memory cell of the plurality of memory cells selected for a read operation to return its resistance to near the initial resistance prior to a read operation of the memory cell.

    摘要翻译： 存储器件包括多个存储器单元，每个存储器单元包括存储单元材料，该存储单元材料具有响应于编程操作中所施加的编程电流而确定的初始电阻，存储单元的电阻从初始电阻变化 编程操作之后的时间段，并且每个存储器单元连接到存储器件的传导线，其用于在编程操作中应用编程电流来对相应的存储器单元的电阻进行编程，并且用于应用编程 读取电流以读取读取操作中的相应存储单元的电阻。 修改电路修改为读取操作选择的多个存储单元的存储单元的电阻，以在存储单元的读取操作之前将其电阻返回到接近初始电阻。

    Multiple level cell phase-change memory device having pre-reading operation resistance drift recovery, memory systems employing such devices and methods of reading memory devices
    5.
    发明申请
    Multiple level cell phase-change memory device having pre-reading operation resistance drift recovery, memory systems employing such devices and methods of reading memory devices 有权
    具有预读取操作电阻漂移恢复的多电平单元相变存储器件，采用这种器件的存储器系统以及读取存储器件的方法

    公开(公告)号：US20080266942A1

    公开(公告)日：2008-10-30

    申请号：US12079869

    申请日：2008-03-28

    申请人： Chang-Wook Jeong ,  Gi-Tae Jeong ,  Hyeong-Jun Kim ,  Seung-Pil Ko

    发明人： Chang-Wook Jeong ,  Gi-Tae Jeong ,  Hyeong-Jun Kim ,  Seung-Pil Ko

    IPC分类号： G11C11/00 ,  G11C7/00

    CPC分类号： G11C11/56 ,  G11C11/5678 ,  G11C13/0004 ,  G11C13/004 ,  G11C13/0069 ,  G11C2013/0078 ,  Y10S977/754

    摘要： A memory device comprises a plurality of memory cells, each memory cell comprising a memory cell material that has an initial resistance that is determined in response to an applied programming current in a programming operation, the resistance of the memory cell varying from the initial resistance over a time period following the programming operation, and each memory cell being connected to a conduction line of the memory device that is used to apply the programming current to program the resistance of the corresponding memory cell in the programming operation and that is used to apply a read current to read the resistance of the corresponding memory cell in a read operation. A modification circuit modifies the resistance of a memory cell of the plurality of memory cells selected for a read operation to return its resistance to near the initial resistance prior to a read operation of the memory cell.

    摘要翻译： 存储器件包括多个存储器单元，每个存储器单元包括存储单元材料，该存储单元材料具有响应于编程操作中所施加的编程电流而确定的初始电阻，存储单元的电阻从初始电阻变化 编程操作之后的时间段，并且每个存储器单元连接到存储器件的传导线，其用于在编程操作中应用编程电流来对相应的存储器单元的电阻进行编程，并且用于应用编程 读取电流以读取读取操作中的相应存储单元的电阻。 修改电路修改为读取操作选择的多个存储单元的存储单元的电阻，以在存储单元的读取操作之前将其电阻返回到接近初始电阻。

    Phase-changeable memory device and method of manufacturing the same
    6.
    发明申请
    Phase-changeable memory device and method of manufacturing the same 审中-公开
    相变存储器件及其制造方法

    公开(公告)号：US20070267669A1

    公开(公告)日：2007-11-22

    申请号：US11783531

    申请日：2007-04-10

    申请人： Hyeong-Jun Kim ,  Byung-Seo Kim

    发明人： Hyeong-Jun Kim ,  Byung-Seo Kim

    IPC分类号： H01L29/94

    CPC分类号： H01L45/143 ,  H01L27/2409 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144 ,  H01L45/1683

    摘要： A phase-changeable memory device may include a substrate including a peripheral region and a cell region, a first pad on the peripheral region, a second pad on the cell region, a lower electrode on the second pad, an insulation layer pattern on the substrate, the insulation layer pattern including a first opening exposing the lower electrode and a second opening exposing the first pad, a phase-changeable layer pattern including a phase-changeable material and being in the first opening, a metal plug in the second opening, the metal plug having an upper surface higher than that of an upper surface of the phase-changeable layer pattern, an upper electrode formed on the phase-changeable layer pattern, and a conductive wiring formed on the metal plug.

    摘要翻译： 相变存储器件可以包括包括外围区域和单元区域的基板，外围区域上的第一焊盘，单元区域上的第二焊盘，第二焊盘上的下部电极，基板上的绝缘层图案 所述绝缘层图案包括暴露所述下电极的第一开口和暴露所述第一焊盘的第二开口，包括相变材料并位于所述第一开口中的相变层图案，所述第二开口中的金属插塞， 具有比相变层图案的上表面高的上表面的金属插塞，形成在相变层图案上的上电极和形成在金属插塞上的导电布线。

    Multiple level cell phase-change memory device having pre-reading operation resistance drift recovery, memory systems employing such devices and methods of reading memory devices
    7.
    发明授权
    Multiple level cell phase-change memory device having pre-reading operation resistance drift recovery, memory systems employing such devices and methods of reading memory devices 有权
    具有预读取操作电阻漂移恢复的多电平单元相变存储器件，采用这种器件的存储器系统以及读取存储器件的方法

    公开(公告)号：US07940552B2

    公开(公告)日：2011-05-10

    申请号：US12079869

    申请日：2008-03-28

    申请人： Jeong Chang-Wook ,  Gi-Tae Jeong ,  Hyeong-Jun Kim ,  Seung-Pil Ko

    发明人： Jeong Chang-Wook ,  Gi-Tae Jeong ,  Hyeong-Jun Kim ,  Seung-Pil Ko

    IPC分类号： G11C11/00

    CPC分类号： G11C11/56 ,  G11C11/5678 ,  G11C13/0004 ,  G11C13/004 ,  G11C13/0069 ,  G11C2013/0078 ,  Y10S977/754

    摘要： A memory device comprises a plurality of memory cells, each memory cell comprising a memory cell material that has an initial resistance that is determined in response to an applied programming current in a programming operation, the resistance of the memory cell varying from the initial resistance over a time period following the programming operation, and each memory cell being connected to a conduction line of the memory device that is used to apply the programming current to program the resistance of the corresponding memory cell in the programming operation and that is used to apply a read current to read the resistance of the corresponding memory cell in a read operation. A modification circuit modifies the resistance of a memory cell of the plurality of memory cells selected for a read operation to return its resistance to near the initial resistance prior to a read operation of the memory cell.

    摘要翻译： 存储器件包括多个存储器单元，每个存储器单元包括存储单元材料，该存储单元材料具有响应于编程操作中所施加的编程电流而确定的初始电阻，存储单元的电阻从初始电阻变化 编程操作之后的时间段，并且每个存储器单元连接到存储器件的传导线，其用于在编程操作中应用编程电流来对相应的存储器单元的电阻进行编程，并且用于应用编程 读取电流以读取读取操作中的相应存储单元的电阻。 修改电路修改为读取操作选择的多个存储单元的存储单元的电阻，以在存储单元的读取操作之前将其电阻返回到接近初始电阻。

    NONVOLATILE MEMORY DEVICE AND SYSTEM, AND METHOD OF PROGRAMMING A NONVOLATILE MEMORY DEVICE
    8.
    发明申请
    NONVOLATILE MEMORY DEVICE AND SYSTEM, AND METHOD OF PROGRAMMING A NONVOLATILE MEMORY DEVICE 有权
    非易失性存储器件和系统，以及非易失性存储器件的编程方法

    公开(公告)号：US20110044104A1

    公开(公告)日：2011-02-24

    申请号：US12859860

    申请日：2010-08-20

    申请人： Dong-Ku Kang ,  Hyeong-Jun Kim

    发明人： Dong-Ku Kang ,  Hyeong-Jun Kim

    IPC分类号： G11C16/04

    CPC分类号： G11C11/5628 ,  G11C16/10 ,  G11C16/3454

    摘要： A method of programming a non-volatile memory including N-bit multi-level cell (MLC) memory includes executing an incremental step pulse programming (ISPP) operation on the MLC memory cells, where the ISPP operation includes a programming sequence of first through Nth page programming operations, where N is an integer of 2 or more. The programming sequence further includes an erase programming that is executed after the (N−1)th page programming operation and before the Nth page programming operation, where the erase page programming increases a threshold voltage distribution of erase cells among the MLC memory cells

    摘要翻译： 一种编程包括N位多电平单元（MLC）存储器的非易失性存储器的方法包括在MLC存储器单元上执行增量步进脉冲编程（ISPP）操作，其中ISPP操作包括第一至第N的编程序列 页编程操作，其中N是2或更大的整数。 编程序列还包括在第（N-1）页编程操作之后和第N页编程操作之前执行的擦除编程，其中擦除页编程增加MLC存储器单元中的擦除单元的阈值电压分布

    Magnetic random access memory cells having split subdigit lines having cladding layers thereon and methods of fabricating the same
    10.
    发明授权
    Magnetic random access memory cells having split subdigit lines having cladding layers thereon and methods of fabricating the same 失效
    磁性随机存取存储单元具有其上具有覆层的分割子数据线及其制造方法

    公开(公告)号：US07569401B2

    公开(公告)日：2009-08-04

    申请号：US12048082

    申请日：2008-03-13

    申请人： Jae-Hyun Park ,  Hyeong-Jun Kim ,  Won-Cheol Jeong ,  Chang-Wook Jeong ,  Hong-sik Jeong ,  Gi-Tae Jeong

    发明人： Jae-Hyun Park ,  Hyeong-Jun Kim ,  Won-Cheol Jeong ,  Chang-Wook Jeong ,  Hong-sik Jeong ,  Gi-Tae Jeong

    IPC分类号： H01L21/00

    CPC分类号： H01L27/228 ,  B82Y10/00 ,  H01L43/08 ,  H01L43/12

    摘要： Magnetic RAM cells have split sub-digit lines surrounded by cladding layers and methods of fabricating the same are provided. The magnetic RAM cells include first and second sub-digit lines formed over a semiconductor substrate. Only a bottom surface and an outer sidewall of the first sub-digit line are covered with a first cladding layer pattern. In addition, only a bottom surface and an outer sidewall of the second sub-digit line are covered with a second cladding layer pattern. The outer sidewall of the first sub-digit line is located distal from the second sub-digit line and the outer sidewall of the second sub-digit line is located distal the first sub-digit line. Methods of fabricating the magnetic RAM cells are also provided.

    摘要翻译： 磁性RAM单元具有由包覆层包围的分割的子数字线，并且提供其制造方法。 磁性RAM单元包括在半导体衬底上形成的第一和第二子数字线。 只有第一子数字线的底表面和外侧壁被第一覆层图案覆盖。 此外，仅第二子数字线的底表面和外侧壁被第二包层图案覆盖。 第一子数字线的外侧壁位于远离第二子数字线的位置，第二子数字线的外侧壁位于第一子数字线的远侧。 还提供了制造磁性RAM单元的方法。