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    Capacitors in integrated circuits and methods of fabrication thereof
    1.
    发明授权
    Capacitors in integrated circuits and methods of fabrication thereof 有权

    公开(公告)号：US10446534B2

    公开(公告)日：2019-10-15

    申请号：US15294698

    申请日：2016-10-15

    Applicant: Infineon Technologies AG

    Inventor： Michael Roehner ,  Stefano Aresu

    IPC: H01L27/01 ,  H01L49/02 ,  H01L23/522 ,  H01L21/70

    Abstract: In one embodiment, a capacitor includes a first row including a first capacitor element and a second capacitor element coupled in parallel, and a second row including a third capacitor element and a fourth capacitor element coupled in parallel. The first row is coupled in series with the second row. In a metallization level over a workpiece, the second capacitor element is disposed between the first capacitor element and the third capacitor element. In the metallization level, the third capacitor element is disposed between the second capacitor element and the fourth capacitor element. The first, the second, the third, and the fourth capacitor elements are disposed in the metallization level.

    Capacitors in integrated circuits and methods of fabrication thereof
    3.
    发明授权
    Capacitors in integrated circuits and methods of fabrication thereof 有权
    集成电路中的电容器及其制造方法

    公开(公告)号：US09508788B2

    公开(公告)日：2016-11-29

    申请号：US13798898

    申请日：2013-03-13

    Applicant: Infineon Technologies AG

    Inventor： Michael Roehner ,  Stefano Aresu

    IPC: H01L21/20 ,  H01L49/02 ,  H01L23/522 ,  H01L27/01

    CPC classification number: H01L27/016 ,  H01L21/707 ,  H01L23/5223 ,  H01L23/5228 ,  H01L28/20 ,  H01L28/40 ,  H01L28/60 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: In one embodiment, a capacitor includes a first row including a first capacitor element and a second capacitor element coupled in parallel, and a second row including a third capacitor element and a fourth capacitor element coupled in parallel. The first row is coupled in series with the second row. In a metallization level over a workpiece, the second capacitor element is disposed between the first capacitor element and the third capacitor element. In the metallization level, the third capacitor element is disposed between the second capacitor element and the fourth capacitor element. The first, the second, the third, and the fourth capacitor elements are disposed in the metallization level.

    Abstract translation: 在一个实施例中，电容器包括第一行，其包括并联耦合的第一电容器元件和第二电容器元件，以及包括并联耦合的第三电容器元件和第四电容器元件的第二行。 第一行与第二行串联耦合。 在工件上的金属化水平中，第二电容器元件设置在第一电容器元件和第三电容器元件之间。 在金属化水平上，第三电容器元件设置在第二电容器元件和第四电容器元件之间。 第一，第二，第三和第四电容器元件设置在金属化水平。

    Circuit and Method for Internally Assessing Dielectric Reliability of a Semiconductor Technology
    4.
    发明申请
    Circuit and Method for Internally Assessing Dielectric Reliability of a Semiconductor Technology 审中-公开
    用于内部评估半导体技术的介质可靠性的电路和方法

    公开(公告)号：US20150194358A1

    公开(公告)日：2015-07-09

    申请号：US14151528

    申请日：2014-01-09

    Applicant: Infineon Technologies AG

    Inventor： Michael Röhner ,  Stefano Aresu ,  Marco Faricelli

    IPC: H01L21/66 ,  G01R31/12 ,  G01R31/26

    CPC classification number: H01L22/34 ,  G01R31/025 ,  G01R31/129 ,  G01R31/2642 ,  G01R31/2894

    Abstract: A semiconductor wafer includes dielectric regions of different thicknesses, some of the dielectric regions being thinner and other ones of the dielectric regions being thicker. The semiconductor wafer further includes a stress circuit operable to stress at least one of the dielectric regions internally within the semiconductor wafer for assessing dielectric reliability. A corresponding method of internally assessing dielectric reliability of a semiconductor technology is also provided.

    Abstract translation: 半导体晶片包括不同厚度的电介质区域，一些电介质区域较薄，其它介质区域较厚。 半导体晶片还包括应力电路，其可操作以在半导体晶片内部应力至少一个电介质区域以评估介电可靠性。 还提供了内部评估半导体技术的介电可靠性的相应方法。

    Capacitors in Integrated Circuits and Methods of Fabrication Thereof
    7.
    发明申请
    Capacitors in Integrated Circuits and Methods of Fabrication Thereof 审中-公开
    集成电路中的电容器及其制造方法

    公开(公告)号：US20170033095A1

    公开(公告)日：2017-02-02

    申请号：US15294698

    申请日：2016-10-15

    Applicant: Infineon Technologies AG

    Inventor： Michael Roehner ,  Stefano Aresu

    IPC: H01L27/01 ,  H01L21/70 ,  H01L49/02

    CPC classification number: H01L27/016 ,  H01L21/707 ,  H01L23/5223 ,  H01L23/5228 ,  H01L28/20 ,  H01L28/40 ,  H01L28/60 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: In one embodiment, a capacitor includes a first row including a first capacitor element and a second capacitor element coupled in parallel, and a second row including a third capacitor element and a fourth capacitor element coupled in parallel. The first row is coupled in series with the second row. In a metallization level over a workpiece, the second capacitor element is disposed between the first capacitor element and the third capacitor element. In the metallization level, the third capacitor element is disposed between the second capacitor element and the fourth capacitor element. The first, the second, the third, and the fourth capacitor elements are disposed in the metallization level.

    Abstract translation: 在一个实施例中，电容器包括第一行，其包括并联耦合的第一电容器元件和第二电容器元件，以及包括并联耦合的第三电容器元件和第四电容器元件的第二行。 第一行与第二行串联耦合。 在工件上的金属化水平中，第二电容器元件设置在第一电容器元件和第三电容器元件之间。 在金属化水平上，第三电容器元件设置在第二电容器元件和第四电容器元件之间。 第一，第二，第三和第四电容器元件设置在金属化水平。

    Capacitors in Integrated Circuits and Methods of Fabrication Thereof
    8.
    发明申请
    Capacitors in Integrated Circuits and Methods of Fabrication Thereof 有权
    集成电路中的电容器及其制造方法

    公开(公告)号：US20140273394A1

    公开(公告)日：2014-09-18

    申请号：US13798898

    申请日：2013-03-13

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： Michael Roehner ,  Stefano Aresu

    IPC: H01L49/02

    CPC classification number: H01L27/016 ,  H01L21/707 ,  H01L23/5223 ,  H01L23/5228 ,  H01L28/20 ,  H01L28/40 ,  H01L28/60 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: In one embodiment, a capacitor includes a first row including a first capacitor element and a second capacitor element coupled in parallel, and a second row including a third capacitor element and a fourth capacitor element coupled in parallel. The first row is coupled in series with the second row. In a metallization level over a workpiece, the second capacitor element is disposed between the first capacitor element and the third capacitor element. In the metallization level, the third capacitor element is disposed between the second capacitor element and the fourth capacitor element. The first, the second, the third, and the fourth capacitor elements are disposed in the metallization level.

    Abstract translation: 在一个实施例中，电容器包括第一行，其包括并联耦合的第一电容器元件和第二电容器元件，以及包括并联耦合的第三电容器元件和第四电容器元件的第二行。 第一行与第二行串联耦合。 在工件上的金属化水平中，第二电容器元件设置在第一电容器元件和第三电容器元件之间。 在金属化水平上，第三电容器元件设置在第二电容器元件和第四电容器元件之间。 第一，第二，第三和第四电容器元件设置在金属化水平。

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