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公开(公告)号：US10304923B2
公开(公告)日：2019-05-28
申请号：US16031799
申请日：2018-07-10
IPC分类号： H01L29/06 , H01L21/768 , H01L29/778 , H01L29/423 , H01L29/20
摘要： A method of manufacturing a semiconductor die includes forming a semiconductor body on a substrate. The semiconductor body has a periphery which is devoid of active devices and terminates at an edge face of the semiconductor die. The semiconductor body includes a first III-nitride semiconductor layer and a plurality of second III-nitride semiconductor layers below the first III-nitride semiconductor layer. The method further includes forming an uninsulated connection structure which extends vertically in the periphery of the semiconductor body and provides a vertical leakage path for at least some of the second III-nitride semiconductor layers either to the substrate or to a metallization layer disposed above the semiconductor body, but not to both. Additional semiconductor die manufacturing methods are provided.
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公开(公告)号：US10038051B2
公开(公告)日：2018-07-31
申请号：US15048809
申请日：2016-02-19
IPC分类号： H01L29/06 , H01L21/768 , H01L29/778 , H01L29/423 , H01L29/20
CPC分类号： H01L29/0607 , H01L21/76879 , H01L29/0657 , H01L29/2003 , H01L29/423 , H01L29/7786
摘要： A semiconductor die includes a substrate and a semiconductor body supported by the substrate and having a periphery which is devoid of active devices and terminates at an edge face of the semiconductor die. The semiconductor body includes a first III-nitride semiconductor layer and a plurality of second III-nitride semiconductor layers below the first III-nitride semiconductor layer. An uninsulated connection structure extends vertically in the periphery of the semiconductor body and provides a vertical leakage path for at least some of the second III-nitride semiconductor layers to the substrate, to a metallization layer disposed above the substrate, or to both. A corresponding method of manufacturing the semiconductor die is also described.
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3.发明申请Method of Manufacturing Semiconductor Devices by Bonding a Semiconductor Disk on a Base Substrate, Composite Wafer and Semiconductor Device 审中-公开通过在基底基板，复合晶片和半导体器件上键合半导体盘来制造半导体器件的方法公开(公告)号：US20160260699A1
公开(公告)日：2016-09-08
申请号：US15052953
申请日：2016-02-25
发明人： Wolfgang Lehnert , Rudolf Berger , Albert Birner , Helmut Brech , Oliver Häberlen , Guenther Ruhl , Roland Rupp
IPC分类号： H01L27/02 , H01L29/16 , H01L21/8258 , H01L29/201 , H01L21/683 , H01L27/06 , H01L21/02 , H01L29/20
CPC分类号： H01L21/8258 , H01L21/2007 , H01L21/6835 , H01L23/481 , H01L27/0694 , H01L27/085 , H01L29/0843 , H01L29/1608 , H01L29/2003 , H01L29/7783 , H01L29/78 , H01L33/0079 , H01L2221/68327 , H01L2221/6835 , H01L2221/68381
摘要： A semiconductor disk of a first crystalline material, which has a first lattice system, is bonded on a process surface of a base substrate, wherein a bonding layer is formed between the semiconductor disk and the base substrate. A second semiconductor layer of a second crystalline material with a second, different lattice system is formed by epitaxy on a first semiconductor layer formed from the semiconductor disk.
摘要翻译： 具有第一晶格系统的第一晶体材料的半导体盘被接合在基底衬底的工艺表面上，其中在半导体盘和基底衬底之间形成接合层。 通过在由半导体盘形成的第一半导体层上外延生长而形成具有第二不同格子系统的第二晶体材料的第二半导体层。
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公开(公告)号：US09356130B2
公开(公告)日：2016-05-31
申请号：US14155926
申请日：2014-01-15
发明人： Gilberto Curatola , Oliver Häberlen
IPC分类号： H01L29/15 , H01L21/338 , H01L29/778 , H01L29/205 , H01L29/417 , H01L29/861 , H01L27/06 , H01L29/66 , H01L29/20
CPC分类号： H01L29/7788 , H01L27/0629 , H01L29/2003 , H01L29/205 , H01L29/41766 , H01L29/66204 , H01L29/66431 , H01L29/66462 , H01L29/7785 , H01L29/7786 , H01L29/861
摘要： A high electron mobility transistor includes a source, a gate and a drain, a first III-V semiconductor region, and a second III-V semiconductor region below the first III-V semiconductor region. The high electron mobility transistor further includes a compensation structure interposed between the first and second III-V semiconductor regions so that the first and second III-V semiconductor regions are spaced apart from one another by the compensation structure. The compensation structure has a different band gap than the first and second III-V semiconductor regions.
摘要翻译： 高电子迁移率晶体管包括源极，栅极和漏极，第一III-V半导体区域和第一III-V半导体区域下方的第二III-V半导体区域。 高电子迁移率晶体管还包括插入在第一和第二III-V半导体区域之间的补偿结构，使得第一和第二III-V半导体区域通过补偿结构彼此间隔开。 补偿结构具有与第一和第二III-V半导体区域不同的带隙。
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公开(公告)号：US09337279B2
公开(公告)日：2016-05-10
申请号：US14195041
申请日：2014-03-03
IPC分类号： H01L21/8249 , H01L29/205 , H01L29/06 , H01L29/20 , H01L29/207 , H01L29/40 , H01L29/417 , H01L29/78
CPC分类号： H01L29/7785 , H01L29/0619 , H01L29/0646 , H01L29/0649 , H01L29/0843 , H01L29/1037 , H01L29/1054 , H01L29/1066 , H01L29/2003 , H01L29/205 , H01L29/207 , H01L29/402 , H01L29/41791 , H01L29/4236 , H01L29/7783 , H01L29/785
摘要： A Group III-nitride-based enhancement mode transistor includes a multi-heterojunction fin structure. A first side face of the multi-heterojunction fin structure is covered by a p-type Group III-nitride layer.
摘要翻译： III族氮化物基增强型晶体管包括多异质结翅片结构。 多异质结翅片结构的第一侧面由p型III族氮化物层覆盖。
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公开(公告)号：US09048303B1
公开(公告)日：2015-06-02
申请号：US14168694
申请日：2014-01-30
IPC分类号： H01L29/78 , H01L29/778 , H01L29/06 , H01L29/423
CPC分类号： H01L29/7786 , H01L29/0646 , H01L29/0657 , H01L29/0688 , H01L29/1066 , H01L29/2003 , H01L29/205 , H01L29/42316 , H01L29/42356 , H01L29/4236 , H01L29/7783 , H01L29/7787
摘要： A Group III-nitride-based enhancement mode transistor includes a heterojunction fin structure. Side faces and a top face of the heterojunction fin structure are covered by a p-type Group III-nitride layer.
摘要翻译： III族氮化物基增强型晶体管包括异质结翅片结构。 异质结翅片结构的侧面和顶面由p型III族氮化物层覆盖。
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公开(公告)号：US20150115326A1
公开(公告)日：2015-04-30
申请号：US14068640
申请日：2013-10-31
IPC分类号： H01L29/20 , H01L29/872 , H01L29/778
CPC分类号： H01L29/2003 , H01L29/42364 , H01L29/7786 , H01L29/7787 , H01L29/872
摘要： In an embodiment, an electronic device includes a semiconductor layer having a surface, a gate and a first current electrode on the surface and a dielectric layer extending between the gate and the first current electrode and including charged ions having a predetermined charge profile.
摘要翻译： 在一个实施例中，电子器件包括在表面上具有表面，栅极和第一电流电极的半导体层以及在栅极和第一电流电极之间延伸的电介质层，并且包括具有预定电荷分布的带电离子。
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公开(公告)号：US20150041984A1
公开(公告)日：2015-02-12
申请号：US13963461
申请日：2013-08-09
发明人： Ralf Otremba , Klaus Schiess , Oliver Häberlen
CPC分类号： H01L24/40 , H01L21/4825 , H01L21/50 , H01L23/48 , H01L23/49513 , H01L23/49562 , H01L23/49568 , H01L23/49575 , H01L24/36 , H01L24/41 , H01L24/84 , H01L2224/05554 , H01L2224/0603 , H01L2224/32245 , H01L2224/40095 , H01L2224/40137 , H01L2224/40245 , H01L2224/4103 , H01L2224/41051 , H01L2224/48247 , H01L2224/73221 , H01L2224/83192 , H01L2224/83801 , H01L2224/84801 , H01L2224/92246 , H01L2924/00014 , H01L2924/10253 , H01L2924/10272 , H01L2924/1033 , H01L2924/1305 , H01L2924/13055 , H01L2924/13063 , H01L2924/13064 , H01L2924/13091 , H01L2924/181 , H01L2924/30107 , H01L2924/00 , H01L2924/00012 , H01L2224/45015 , H01L2924/207 , H01L2224/45099 , H01L2224/37099
摘要： An electronic component includes a high-voltage depletion-mode transistor, a low-voltage enhancement-mode transistor arranged adjacent and spaced apart from the high-voltage depletion-mode transistor, and an electrically conductive member electrically coupling a first current electrode of the high-voltage depletion-mode transistor to a first current electrode of the low-voltage enhancement-mode transistor. The electrically conductive member has a sheet-like form.
摘要翻译： 电子部件包括高压耗尽型晶体管，与高电压耗尽型晶体管相邻且间隔开的低电压增强型晶体管，以及电连接高电压耗尽型晶体管的第一电流电极的导电部件 电压耗尽型晶体管连接到低电压增强型晶体管的第一电流电极。 导电构件具有片状形式。
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公开(公告)号：US11114554B2
公开(公告)日：2021-09-07
申请号：US15635695
申请日：2017-06-28
IPC分类号： H01L29/778 , H01L29/40 , H01L29/205 , H01L29/10 , H01L21/02 , H01L21/306 , H01L29/06 , H01L29/20 , H01L29/66
摘要： A high-electron-mobility semiconductor device includes: a buffer region having first, second and third cross-sections forming a stepped lateral profile, the first cross-section being thicker than the third cross-section and comprising a first buried field plate disposed therein, the second cross-section interposed between the first and third cross-sections and forming oblique angles with the first and third cross-sections; and a barrier region of substantially uniform thickness extending along the stepped lateral profile of the buffer region, the barrier region being separated from the first buried field plate by a portion of the buffer region. The buffer region is formed by a first semiconductor material and the barrier region is formed by a second semiconductor material. The first and second semiconductor materials have different band-gaps such that an electrically conductive channel including a two-dimensional charge carrier gas arises at an interface between the buffer and barrier regions due to piezoelectric effects.
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公开(公告)号：US10600710B2
公开(公告)日：2020-03-24
申请号：US16206372
申请日：2018-11-30
IPC分类号： H01L29/423 , H01L23/31 , H01L29/778 , H01L29/51 , H01L29/10 , H01L29/20 , H01L29/207
摘要： A semiconductor device includes a group III-semiconductor-nitride-based channel layer, a group III-semiconductor-nitride-based barrier layer formed on the channel layer, a two-dimensional electron gas channel formed in the channel layer, a first current electrode and a second current electrode formed on the barrier layer and laterally spaced from each other, and a gate structure formed on the barrier layer between the first and second current electrodes. The barrier layer has a symmetrically shaped recess between the first and second current electrodes, the symmetrically shaped recess including a first recess portion formed in a part of an upper surface of the barrier layer and a second recess portion formed within the first recess portion. The gate structure includes a group III-semiconductor-nitride-based doped layer that fills the symmetrically shaped recess and an electrically conductive gate electrode formed on an upper side of the doped layer that is opposite from the barrier layer.
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