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    BALANCING ENERGY BARRIER BETWEEN STATES IN PERPENDICULAR MAGNETIC TUNNEL JUNCTIONS
    3.
    发明申请
    BALANCING ENERGY BARRIER BETWEEN STATES IN PERPENDICULAR MAGNETIC TUNNEL JUNCTIONS 审中-公开
    平衡磁性隧道结状态之间的平衡能量障碍

    公开(公告)号：US20160126452A1

    公开(公告)日：2016-05-05

    申请号：US14992601

    申请日：2016-01-11

    Applicant: INTEL CORPORATION

    Inventor： CHARLES C. KUO ,  BRIAN S. DOYLE ,  Arijit Raychowdhury ,  ROKSANA GOLIZADEH MOJARAD ,  KAAN OGUZ

    IPC: H01L43/02 ,  H01L43/12

    CPC classification number: H01L43/02 ,  G11C11/161 ,  G11C11/1673 ,  G11C11/1675 ,  H01L43/08 ,  H01L43/12

    Abstract: Techniques are disclosed for enhancing performance of a perpendicular magnetic tunnel junction (MTJ) by implementing an additional ferromagnetic layer therein. The additional ferromagnetic layer can be implemented, for example, in or otherwise proximate either the fixed ferromagnetic layer or the free ferromagnetic layer of the perpendicular MTJ. In some embodiments, the additional ferromagnetic layer is implemented with a non-magnetic spacer, wherein the thickness of the additional ferromagnetic layer and/or spacer can be adjusted to sufficiently balance the energy barrier between parallel and anti-parallel states of the perpendicular MTJ. In some embodiments, the additional ferromagnetic layer is configured such that its magnetization is opposite that of the fixed ferromagnetic layer.

    Abstract translation: 公开了通过在其中实现附加铁磁层来增强垂直磁隧道结（MTJ）的性能的技术。 附加铁磁层可以例如在垂直MTJ的固定铁磁层或自由铁磁层中或以其它方式实现。 在一些实施例中，附加铁磁层用非磁性间隔件实现，其中可以调整附加铁磁层和/或间隔物的厚度以使垂直MTJ的平行和反平行状态之间的能量势垒充分平衡。 在一些实施例中，附加铁磁层被配置为使得其磁化强度与固定铁磁层的磁化强度相反。

    Spin transfer torque based memory elements for programmable device arrays
    5.
    发明授权
    Spin transfer torque based memory elements for programmable device arrays 有权
    用于可编程器件阵列的基于转移转矩的存储元件

    公开(公告)号：US09577641B2

    公开(公告)日：2017-02-21

    申请号：US15016260

    申请日：2016-02-04

    Applicant: Intel Corporation

    Inventor： Arijit Raychowdhury ,  James W. Tschanz ,  Vivek De

    IPC: H03K19/177 ,  G11C11/16

    CPC classification number: H03K19/17728 ,  G11C11/16 ,  H03K19/177

    Abstract: Disclosed herein are semiconductor device arrays, such as, Field Programmable Gate Arrays (FPGAs) and Complex Programmable Logic Arrays (CPLAs) that use high-density Spin Transfer Torque (STT)-based memory elements. STT-based memory elements can either be stand-alone FPGAs/CPLAs, or can be embedded in microprocessors and/or digital signal processing (DSP) system-on-chip (SoC) to provide design flexibility for implementing low power, scalable, secure and reconfigurable hardware architecture. Because the configuration is stored on the FPGA/CPLA die itself, the need for loading the configuration from external storage every time is eliminated when the device is powered on. In addition to instant startup, eliminating configuration I/O traffic results in power savings and possible pin count reduction. Security is greatly improved by eliminating the need to store configuration data in an external memory.

    Abstract translation: 这里公开了使用基于高密度旋转转矩（STT）的存储器元件的半导体器件阵列，诸如现场可编程门阵列（FPGA）和复数可编程逻辑阵列（CPLAs）。 基于STT的存储器元件可以是独立的FPGA / CPLAs，或者可以嵌入在微处理器和/或数字信号处理（DSP）片上系统（SoC）中，以提供设计灵活性，以实现低功率，可扩展，安全 和可重构硬件架构。 由于配置存储在FPGA / CPLA裸片本身，所以每次在外部存储器上加载配置的需求都将在设备通电时被消除。 除了即时启动，消除配置I / O流量导致节电和可能的引脚数减少。 通过消除将配置数据存储在外部存储器中的需要，安全性大大提高。

    DIGITAL CLAMP FOR STATE RETENTION
    6.
    发明申请
    DIGITAL CLAMP FOR STATE RETENTION 审中-公开
    用于国家保留的数字钳

    公开(公告)号：US20170041001A1

    公开(公告)日：2017-02-09

    申请号：US15331280

    申请日：2016-10-21

    Applicant: INTEL CORPORATION

    Inventor： Arijit Raychowdhury ,  Charles Augustine ,  James W. Tschanz ,  Vivek K. De

    IPC: H03K19/00 ,  G06F1/32 ,  H03K3/037

    CPC classification number: H03K19/0016 ,  G05F1/10 ,  G05F1/461 ,  G05F1/59 ,  G06F1/3287 ,  G06F1/3296 ,  H03K3/0377 ,  H03K19/0008

    Abstract: Described is an apparatus which comprises: a clamp coupled between a first power supply and a second power supply, the clamp including a plurality of transistors, a circuit to operate with the second power supply; and a control unit to turn on and off the plurality of transistors to adjust the second power supply when the apparatus enters a low power mode. The control unit includes a first comparator to compare the second power supply with a first reference, a second comparator to compare the second power supply with a second reference, and a counter. The counter counts up when the second power supply is higher than the first reference and counts down when the second power supply is lower than the second reference.

    Abstract translation: 描述了一种装置，其包括：夹紧器，其耦合在第一电源和第二电源之间，所述夹具包括多个晶体管，用于与所述第二电源一起操作的电路; 以及控制单元，用于在所述设备进入低功率模式时接通和断开所述多个晶体管以调节所述第二电源。 控制单元包括用于将第二电源与第一参考值进行比较的第一比较器，将第二电源与第二参考电压进行比较的第二比较器和计数器。 当第二电源高于第一个参考电压时，计数器递增计数，当第二个电源低于第二个参考电压时，计数器递减计数。

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