公开(公告)号：US20230420514A1

公开(公告)日：2023-12-28

申请号：US17852016

申请日：2022-06-28

Applicant: Intel Corporation

Inventor： Chelsey DOROW ,  Sudarat LEE ,  Kevin P. O'BRIEN ,  Ande KITAMURA ,  Ashish Verma PENUMATCHA ,  Carl H. NAYLOR ,  Kirby MAXEY ,  Scott B. CLENDENNING ,  Uygar E. AVCI ,  Chia-Ching LIN

IPC: H01L29/06 ,  H01L29/423 ,  H01L29/18 ,  H01L29/786 ,  H01L29/778

CPC classification number: H01L29/0673 ,  H01L29/42392 ,  H01L29/18 ,  H01L29/78696 ,  H01L29/778

Abstract: Embodiments disclosed herein include transistor devices. In an embodiment, the transistor comprises a transition metal dichalcogenide (TMD) channel. In an embodiment, a two dimensional (2D) dielectric is over the TMD channel. In an embodiment, a gate metal is over the 2D dielectric.

公开(公告)号：US20230411443A1

公开(公告)日：2023-12-21

申请号：US18129258

申请日：2023-03-31

Applicant: Intel Corporation

Inventor： Kaan OGUZ ,  Chia-Ching LIN ,  Arnab SEN GUPTA ,  I-Cheng TUNG ,  Sou-Chi CHANG ,  Sudarat LEE ,  Matthew V. METZ ,  Uygar E. AVCI ,  Scott B. CLENDENNING ,  Ian A. YOUNG

IPC: H01L21/02 ,  H01L23/522 ,  H01L23/00

CPC classification number: H01L28/56 ,  H01L28/92 ,  H01L28/91 ,  H01L28/75 ,  H01L23/5223 ,  H01L23/5226 ,  H01L24/32 ,  H01L28/65 ,  H01L2224/32225 ,  H01L24/73 ,  H01L2224/16227 ,  H01L24/16 ,  H01L2224/73204

Abstract: Metal insulator metal capacitors are described. In an example, a metal-insulator-metal (MIM) capacitor includes a first electrode. An insulator is over the first electrode. The insulator includes a first layer, and a second layer over the first layer. The first layer has a leakage current that is less than a leakage current of the second layer. The second layer has a dielectric constant that is greater than a dielectric constant of the first layer. A second electrode is over the insulator.

公开(公告)号：US20200058548A1

公开(公告)日：2020-02-20

申请号：US16347507

申请日：2016-12-23

Applicant: Intel Corporation

Inventor： Eungnak HAN ,  Rami HOURANI ,  Florian GSTREIN ,  Gurpreet SINGH ,  Scott B. CLENDENNING ,  Kevin L. LIN ,  Manish CHANDHOK

IPC: H01L21/768 ,  H01L21/311 ,  H01L21/033 ,  H01L23/522

Abstract: Selective hardmask-based approaches for conductive via fabrication are described. In an example, an integrated circuit structure includes a plurality of conductive lines in an inter-layer dielectric (ILD) layer above a substrate. The plurality of conductive lines includes alternating non-recessed conductive lines and recessed conductive lines. The non-recessed conductive lines are substantially co-planar with the ILD layer, and the recessed conductive lines are recessed relative to an uppermost surface of the ILD layer. A dielectric capping layer is in recess regions above the recessed conductive lines. A hardmask layer is over the non-recessed conductive lines but not over the dielectric capping layer of the recessed conductive lines. The hardmask layer differs in composition from the dielectric capping layer. A conductive via is in an opening in the dielectric capping layer and on one of the recessed conductive lines. A portion of the conductive via is on a portion of the hardmask layer.

公开(公告)号：US20190252511A1

公开(公告)日：2019-08-15

申请号：US15772783

申请日：2015-12-09

Applicant: Intel Corporation

Inventor： Scott B. CLENDENNING ,  Han Wui THEN ,  John J. PLOMBON ,  Michael L. MCSWINEY

IPC: H01L29/49 ,  H01L27/088 ,  H01L21/285 ,  H01L23/532

CPC classification number: H01L29/4966 ,  C23C16/30 ,  H01L21/28088 ,  H01L21/28556 ,  H01L21/76843 ,  H01L23/53209 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53252 ,  H01L23/53266 ,  H01L27/0886

Abstract: Embodiments of the present disclosure describe semiconductor devices with ruthenium phosphorus thin films and further describe the processes to deposit the thin films. The thin films may be deposited in a gate stack of a transistor device or in an interconnect structure. The processes to deposit the films may include chemical vapor deposition and may include ruthenium precursors. The precursors may contain phosphorus. A co-reactant may be used during deposition. A co-reactant may include a phosphorus based compound. A gate material may be deposited on the film in a gate stack. The ruthenium phosphorus film may be a metal diffusion barrier and an adhesion layer, and the film may be a work function metal for some embodiments. Other embodiments may be described and/or claimed.

公开(公告)号：US20180151684A1

公开(公告)日：2018-05-31

申请号：US15576253

申请日：2015-06-27

Applicant: Intel Corporation

Inventor： Benjamin CHU-KUNG ,  Van H. LE ,  Rafael RIOS ,  Gilbert DEWEY ,  Scott B. CLENDENNING ,  Jack T. KAVALIEROS

IPC: H01L29/45 ,  H01L21/768 ,  H01L21/285 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/45 ,  H01L21/28556 ,  H01L21/28568 ,  H01L21/76802 ,  H01L21/76883 ,  H01L23/49827 ,  H01L23/49838 ,  H01L29/0847 ,  H01L29/41783 ,  H01L29/66568 ,  H01L29/78

Abstract: An apparatus including an integrated circuit device including at least one low density of state metal/semiconductor material interface, wherein the at least one low density of state metal is quantized. An apparatus including an integrated circuit device including at least one interface of a low density of state metal and a semiconductor material, wherein a contact area of the metal at the interface is graded. A method including confining a contact area of a semiconductor material; and forming a metal contact in the contact area.

公开(公告)号：US20230420511A1

公开(公告)日：2023-12-28

申请号：US17850623

申请日：2022-06-27

Applicant: Intel Corporation

Inventor： Carl H. NAYLOR ,  Kirby MAXEY ,  Kevin P. O'BRIEN ,  Chelsey DOROW ,  Sudarat LEE ,  Ashish Verma PENUMATCHA ,  Uygar E. AVCI ,  Matthew V. METZ ,  Scott B. CLENDENNING ,  Chia-Ching LIN ,  Carly ROGAN ,  Arnab SEN GUPTA

IPC: H01L29/06 ,  H01L29/778 ,  H01L29/786 ,  H01L29/18 ,  H01L21/02

CPC classification number: H01L29/0673 ,  H01L29/778 ,  H01L29/78696 ,  H01L21/02568 ,  H01L21/02645 ,  H01L21/02598 ,  H01L21/02485 ,  H01L29/18

Abstract: Embodiments described herein may be related to apparatuses, processes, systems, and/or techniques for a transistor structure that includes stacked nanoribbons as a single crystal or monolayer, such as a transition metal dichalcogenide (TMD) layer, grown on a silicon wafer using a seeding material. Other embodiments may be described and/or claimed.

公开(公告)号：US20220199760A1

公开(公告)日：2022-06-23

申请号：US17129875

申请日：2020-12-21

Applicant: Intel Corporation

Inventor： Abhishek A. SHARMA ,  Noriyuki SATO ,  Sudarat LEE ,  Scott B. CLENDENNING ,  Sudipto NASKAR ,  Manish CHANDHOK ,  Hui Jae YOO ,  Van H. LE

IPC: H01L49/02 ,  H01L23/522 ,  H01L23/528 ,  H01G4/10

Abstract: An integrated circuit (IC) structure having a plurality of backend double-walled capacitors (DWCs) are described. In an example, a first interconnect layer is disposed over a substrate and a second interconnect layer is disposed over the first interconnect layer. In the example, a plurality of DWCs are disposed in the first interconnect layer or the second interconnect layer to provide capacitance to assist the first interconnect layer and the second interconnect layer in providing electrical signal routing and power distribution to one or more devices in the IC structure. In examples, the IC structure includes a logic IC or a coupling substrate.

公开(公告)号：US20210091075A1

公开(公告)日：2021-03-25

申请号：US16579055

申请日：2019-09-23

Applicant: Intel Corporation

Inventor： Szuya S. LIAO ,  Scott B. CLENDENNING ,  Jessica TORRES ,  Lukas BAUMGARTEL ,  Kiran CHIKKADI ,  Diane LANCASTER ,  Matthew V. METZ ,  Florian GSTREIN ,  Martin M. MITAN ,  Rami HOURANI

IPC: H01L27/088 ,  H01L29/423

Abstract: Self-aligned gate endcap (SAGE) architectures without fin end gaps, and methods of fabricating self-aligned gate endcap (SAGE) architectures without fin end gaps, are described. In an example, an integrated circuit structure includes a semiconductor fin having a cut along a length of the semiconductor fin. A gate endcap isolation structure has a first portion parallel with the length of the semiconductor fin and is spaced apart from the semiconductor fin. The gate endcap isolation structure also has a second portion in a location of the cut of the semiconductor fin and in contact with the semiconductor fin.

公开(公告)号：US20200168462A1

公开(公告)日：2020-05-28

申请号：US16637177

申请日：2017-09-27

Applicant: Intel Corporation

Inventor： Patricio E. ROMERO ,  Scott B. CLENDENNING ,  Florian GSTREIN ,  Cen TAN

IPC: H01L21/28 ,  H01L21/02 ,  H01L29/51 ,  H01L21/306

Abstract: Embodiments herein describe techniques for a semiconductor device including a Ge substrate. A passivation layer may be formed above the Ge substrate, where the passivation layer may include one or more molecular monolayers with atoms of one or more group 15 elements or group 16 elements. In addition, a low-k interlayer may be above the passivation layer, and a high-k interlayer may be above the low-k interlayer. Furthermore, a metal contact may be above the high-k interlayer. Other embodiments may be described and/or claimed.

公开(公告)号：US20180219080A1

公开(公告)日：2018-08-02

申请号：US15506101

申请日：2014-09-26

Applicant: INTEL CORPORATION

Inventor： Scott B. CLENDENNING ,  Szuya S. LIAO ,  Florian GSTREIN ,  Rami HOURANI ,  Patricio E. ROMERO ,  Grant M. KLOSTER ,  Martin M. MITAN

IPC: H01L29/66 ,  H01L29/06 ,  H01L29/423 ,  H01L29/49 ,  H01L21/28

CPC classification number: H01L29/66545 ,  H01L21/265 ,  H01L21/266 ,  H01L21/28247 ,  H01L29/0673 ,  H01L29/42364 ,  H01L29/42392 ,  H01L29/4983 ,  H01L29/51 ,  H01L29/66439 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/785

Abstract: Techniques related to forming selective gate spacers for semiconductor devices and transistor structures and devices formed using such techniques are discussed. Such techniques include forming a blocking material on a semiconductor fin, disposing a gate having a different surface chemistry than the blocking material on a portion of the blocking material, forming a selective conformal layer on the gate but not on a portion of the blocking material, and removing exposed portions of the blocking material.