公开(公告)号：US20240014138A1

公开(公告)日：2024-01-11

申请号：US18139862

申请日：2023-04-26

Applicant: Intel Corporation

Inventor： Yueli LIU ,  Qinglei ZHANG ,  Amanda E. SCHUCKMAN ,  Rui ZHANG

IPC: H01L23/538 ,  H01L23/498 ,  H01L23/00 ,  H05K1/11 ,  H01L25/065

CPC classification number: H01L23/5381 ,  H01L23/49816 ,  H01L24/08 ,  H05K1/111 ,  H01L23/49822 ,  H01L25/0655 ,  H01L2924/1433 ,  H01L2924/1434 ,  H01L2924/01029 ,  H01L2924/01028 ,  H01L2224/08146 ,  H01L2224/08165 ,  H01L2924/014

Abstract: Embodiments of the present disclosure are directed towards techniques and configurations for layered interconnect structures for bridge interconnection in integrated circuit assemblies. In one embodiment, an apparatus may include a substrate and a bridge embedded in the substrate. The bridge may be configured to route electrical signals between two dies. An interconnect structure, electrically coupled with the bridge, may include a via structure including a first conductive material, a barrier layer including a second conductive material disposed on the via structure, and a solderable material including a third conductive material disposed on the barrier layer. The first conductive material, the second conductive material, and the third conductive material may have different chemical composition. Other embodiments may be described and/or claimed.

公开(公告)号：US20250112164A1

公开(公告)日：2025-04-03

申请号：US18374932

申请日：2023-09-29

Applicant: Intel Corporation

Inventor： Bohan SHAN ,  Onur OZKAN ,  Ryan CARRAZZONE ,  Rui ZHANG ,  Haobo CHEN ,  Ziyin LIN ,  Yiqun BAI ,  Kyle ARRINGTON ,  Jose WAIMIN ,  Hongxia FENG ,  Srinivas Venkata Ramanuja PIETAMBARAM ,  Gang DUAN ,  Dingying David XU ,  Bin MU ,  Mohit GUPTA ,  Jeremy D. ECTON ,  Brandon C. MARIN ,  Xiaoying GUO ,  Steve S. CHO ,  Ali LEHAF ,  Venkata Rajesh SARANAM ,  Shripad GOKHALE ,  Kartik SRINIVASAN ,  Edvin CETEGEN ,  Mine KAYA ,  Nicholas S. HAEHN ,  Deniz TURAN

IPC: H01L23/538 ,  H01L21/48 ,  H01L23/00 ,  H01L25/065

Abstract: A device comprises a substrate comprising a plurality of build-up layers and a cavity. A bridge die is located within the cavity and a plurality of cavity side bumps are on one side of the bridge die. A plurality of interconnect pads with variable heights are on one of the build-up layers of the substrate coupled to the plurality of the cavity side bumps to bond the bridge die to the substrate.

公开(公告)号：US20250015004A1

公开(公告)日：2025-01-09

申请号：US18894586

申请日：2024-09-24

Applicant: Intel Corporation

Inventor： Yueli LIU ,  Qinglei ZHANG ,  Amanda E. SCHUCKMAN ,  Rui ZHANG

IPC: H01L23/538 ,  H01L23/00 ,  H01L23/532 ,  H01L25/065 ,  H01L25/18 ,  H05K1/18 ,  H05K3/34

Abstract: Embodiments of the present disclosure are directed towards techniques and configurations for layered interconnect structures for bridge interconnection in integrated circuit assemblies. In one embodiment, an apparatus may include a substrate and a bridge embedded in the substrate. The bridge may be configured to route electrical signals between two dies. An interconnect structure, electrically coupled with the bridge, may include a via structure including a first conductive material, a barrier layer including a second conductive material disposed on the via structure, and a solderable material including a third conductive material disposed on the barrier layer. The first conductive material, the second conductive material, and the third conductive material may have different chemical composition. Other embodiments may be described and/or claimed.

公开(公告)号：US20210384129A1

公开(公告)日：2021-12-09

申请号：US17410716

申请日：2021-08-24

Applicant: Intel Corporation

Inventor： Yueli LIU ,  Qinglei ZHANG ,  Amanda E. SCHUCKMAN ,  Rui ZHANG

IPC: H01L23/538 ,  H01L23/00 ,  H01L25/065 ,  H05K1/18 ,  H01L23/532 ,  H01L25/18

Abstract: Embodiments of the present disclosure are directed towards techniques and configurations for layered interconnect structures for bridge interconnection in integrated circuit assemblies. In one embodiment, an apparatus may include a substrate and a bridge embedded in the substrate. The bridge may be configured to route electrical signals between two dies. An interconnect structure, electrically coupled with the bridge, may include a via structure including a first conductive material, a barrier layer including a second conductive material disposed on the via structure, and a solderable material including a third conductive material disposed on the barrier layer. The first conductive material, the second conductive material, and the third conductive material may have different chemical composition. Other embodiments may be described and/or claimed.