公开(公告)号：US20240014138A1

公开(公告)日：2024-01-11

申请号：US18139862

申请日：2023-04-26

Applicant: Intel Corporation

Inventor： Yueli LIU ,  Qinglei ZHANG ,  Amanda E. SCHUCKMAN ,  Rui ZHANG

IPC: H01L23/538 ,  H01L23/498 ,  H01L23/00 ,  H05K1/11 ,  H01L25/065

CPC classification number: H01L23/5381 ,  H01L23/49816 ,  H01L24/08 ,  H05K1/111 ,  H01L23/49822 ,  H01L25/0655 ,  H01L2924/1433 ,  H01L2924/1434 ,  H01L2924/01029 ,  H01L2924/01028 ,  H01L2224/08146 ,  H01L2224/08165 ,  H01L2924/014

Abstract: Embodiments of the present disclosure are directed towards techniques and configurations for layered interconnect structures for bridge interconnection in integrated circuit assemblies. In one embodiment, an apparatus may include a substrate and a bridge embedded in the substrate. The bridge may be configured to route electrical signals between two dies. An interconnect structure, electrically coupled with the bridge, may include a via structure including a first conductive material, a barrier layer including a second conductive material disposed on the via structure, and a solderable material including a third conductive material disposed on the barrier layer. The first conductive material, the second conductive material, and the third conductive material may have different chemical composition. Other embodiments may be described and/or claimed.

公开(公告)号：US20210384129A1

公开(公告)日：2021-12-09

申请号：US17410716

申请日：2021-08-24

Applicant: Intel Corporation

Inventor： Yueli LIU ,  Qinglei ZHANG ,  Amanda E. SCHUCKMAN ,  Rui ZHANG

IPC: H01L23/538 ,  H01L23/00 ,  H01L25/065 ,  H05K1/18 ,  H01L23/532 ,  H01L25/18

Abstract: Embodiments of the present disclosure are directed towards techniques and configurations for layered interconnect structures for bridge interconnection in integrated circuit assemblies. In one embodiment, an apparatus may include a substrate and a bridge embedded in the substrate. The bridge may be configured to route electrical signals between two dies. An interconnect structure, electrically coupled with the bridge, may include a via structure including a first conductive material, a barrier layer including a second conductive material disposed on the via structure, and a solderable material including a third conductive material disposed on the barrier layer. The first conductive material, the second conductive material, and the third conductive material may have different chemical composition. Other embodiments may be described and/or claimed.

公开(公告)号：US20250015004A1

公开(公告)日：2025-01-09

申请号：US18894586

申请日：2024-09-24

Applicant: Intel Corporation

Inventor： Yueli LIU ,  Qinglei ZHANG ,  Amanda E. SCHUCKMAN ,  Rui ZHANG

IPC: H01L23/538 ,  H01L23/00 ,  H01L23/532 ,  H01L25/065 ,  H01L25/18 ,  H05K1/18 ,  H05K3/34

Abstract: Embodiments of the present disclosure are directed towards techniques and configurations for layered interconnect structures for bridge interconnection in integrated circuit assemblies. In one embodiment, an apparatus may include a substrate and a bridge embedded in the substrate. The bridge may be configured to route electrical signals between two dies. An interconnect structure, electrically coupled with the bridge, may include a via structure including a first conductive material, a barrier layer including a second conductive material disposed on the via structure, and a solderable material including a third conductive material disposed on the barrier layer. The first conductive material, the second conductive material, and the third conductive material may have different chemical composition. Other embodiments may be described and/or claimed.

公开(公告)号：US20190189582A1

公开(公告)日：2019-06-20

申请号：US16328135

申请日：2016-10-01

Applicant: Intel Corporation

Inventor： Kyu Oh LEE ,  Yi LI ,  Yueli LIU

IPC: H01L23/00 ,  H01L23/498

CPC classification number: H01L24/16 ,  B23K35/0238 ,  B23K35/0244 ,  B23K35/24 ,  B23K35/262 ,  C22C13/00 ,  H01L23/00 ,  H01L23/49816 ,  H01L23/49866 ,  H01L24/13 ,  H01L24/81 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13155 ,  H01L2224/13247 ,  H01L2224/16227 ,  H01L2224/81203 ,  H01L2224/81815 ,  H01L2924/01029 ,  H01L2924/01049 ,  H01L2924/014 ,  H01L2924/01047

Abstract: Embodiments are generally directed to indium solder metallurgy to control electro-migration. An embodiment of an electronic device includes a die; and a package substrate, wherein the die is bonded to the package substrate by an interconnection. The interconnection includes multiple interconnects, and wherein the interconnection includes a solder. The solder for the interconnection includes a combination of tin (Sn), copper (Cu), and indium (In).

公开(公告)号：US20150318238A1

公开(公告)日：2015-11-05

申请号：US14798395

申请日：2015-07-13

Applicant: Intel Corporation

Inventor： Mark S. HLAD ,  Islam A. SALAMA ,  Mihir K. ROY ,  Tao WU ,  Yueli LIU ,  Kyu Oh LEE

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/50 ,  H01L21/48

CPC classification number: H01L23/49838 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/563 ,  H01L23/49811 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49866 ,  H01L23/50 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L2224/1112 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/11466 ,  H01L2224/119 ,  H01L2224/13005 ,  H01L2224/13082 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/1601 ,  H01L2224/16225 ,  H01L2224/16238 ,  H01L2224/165 ,  H01L2224/2919 ,  H01L2224/73204 ,  H01L2224/81121 ,  H01L2224/81191 ,  H01L2224/81444 ,  H01L2224/81455 ,  H01L2224/81464 ,  H01L2224/81815 ,  H01L2224/831 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01046 ,  H01L2924/01079 ,  H01L2924/01103 ,  H01L2924/01108 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15321 ,  H01L2924/2064 ,  H01L2924/37001 ,  H01L2924/3841 ,  H05K1/113 ,  H05K3/107 ,  H05K3/3436 ,  H05K3/421 ,  H01L2924/00014 ,  H01L2924/00

Abstract: Package substrates enabling reduced bump pitches and package assemblies thereof. Surface-level metal features are embedded in a surface-level dielectric layer with surface finish protruding from a top surface of the surface-level dielectric for assembly, without solder resist, to an IC chip having soldered connection points. Package substrates are fabricated to enable multiple levels of trace routing with each trace routing level capable of reduced minimum trace width and spacing.

Abstract translation: 封装衬底，能够减少凸起间距和封装组件。 表面级金属特征嵌入表面级电介质层中，其表面光洁度从表面电介质的顶表面突出，用于组装而无阻焊，具有焊接连接点的IC芯片。 制造封装衬底以实现多级跟踪路由，每个跟踪路由级别能够减少最小迹线宽度和间距。