公开(公告)号：US20170040211A1

公开(公告)日：2017-02-09

申请号：US14821647

申请日：2015-08-07

Applicant: INTEL CORPORATION

Inventor： Zheng Zhou ,  Amanda E. Schuckman ,  Sri Ranga Sai Boyapati

IPC: H01L21/768 ,  H01L23/532 ,  H01L23/528 ,  H01L23/522

CPC classification number: H01L21/76814 ,  H01L21/486 ,  H01L21/76804 ,  H01L21/76816 ,  H01L21/76879 ,  H01L23/145 ,  H01L23/49822 ,  H01L23/49827

Abstract: Embodiments herein may relate to a technique for generating a via in a substrate. Specifically, the technique may include coupling a polyethylene terephthalate (PET) layer, a protective metal layer, and a build-up layer to a metal layer. The process may further include etching a via in the PET layer, the protective metal layer, and at least a portion of the build-up layer. The process may further include performing a plasma desmear process on the substrate and then peeling the PET layer to remove the PET layer and the protective metal layer. Other embodiments may be described and/or claimed.

Abstract translation: 本文的实施例可以涉及用于在衬底中产生通孔的技术。 具体地，该技术可以包括将聚对苯二甲酸乙二醇酯（PET）层，保护金属层和堆积层耦合到金属层。 该方法还可以包括在PET层，保护性金属层和至少一部分积聚层中蚀刻通孔。 该方法可以进一步包括在衬底上执行等离子体去污工艺，然后剥离PET层以除去PET层和保护金属层。 可以描述和/或要求保护其他实施例。

公开(公告)号：US09505607B2

公开(公告)日：2016-11-29

申请号：US14671549

申请日：2015-03-27

Applicant: Intel Corporation

Inventor： Kyu Oh Lee ,  Zheng Zhou ,  Islam A. Salama ,  Feras Eid ,  Sasha N. Oster ,  Lay Wai Kong ,  Javier Soto Gonzalez

IPC: B81B3/00 ,  B81C1/00

CPC classification number: B81B7/0077 ,  B81C2203/0109

Abstract: Methods of forming sensor integrated package devices and structures formed thereby are described. An embodiment includes providing a substrate core, wherein a first conductive trace structure and a second conductive trace structure are disposed on the substrate core, forming a cavity between the first conductive trace structure and the second conductive trace structure, and placing a magnet on a resist material disposed on a portion of each of the first and second conductive trace structures, wherein the resist material does not extend over the cavity.

Abstract translation: 描述形成传感器集成封装器件和由此形成的结构的方法。 一个实施例包括提供衬底芯，其中第一导电迹线结构和第二导电迹线结构设置在衬底芯上，在第一导电迹线结构和第二导电迹线结构之间形成空腔，并将磁体放置在抗蚀剂上 设置在第一和第二导电迹线结构中的每一个的一部分上的材料，其中抗蚀剂材料不在空腔上延伸。

公开(公告)号：US20170103941A1

公开(公告)日：2017-04-13

申请号：US15028278

申请日：2015-05-13

Applicant: INTEL CORPORATION

Inventor： Zheng Zhou ,  Mihir K. Roy ,  Chong Zhang ,  Kyu-Oh Lee ,  Amanda E. Schuckman

IPC: H01L23/498 ,  H01L21/768 ,  H01L23/00

CPC classification number: H01L23/49827 ,  H01L21/76804 ,  H01L21/76879 ,  H01L23/145 ,  H01L23/49838 ,  H01L23/66 ,  H01L24/14 ,  H01L2223/6616 ,  H01L2223/6677 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/15311

Abstract: Some embodiments of the present disclosure describe a multi-layer package with a bi-layered dielectric structure and associated techniques and configurations. In one embodiment, an integrated circuit (IC) package assembly includes a dielectric structure coupled with a metal layer, with the dielectric structure including a first dielectric layer and a second dielectric layer, wherein the first dielectric layer has a thickness less than a thickness of the second dielectric layer and a dielectric loss tangent greater than a dielectric loss tangent of the second layer. Other embodiments may be described and/or claimed.

公开(公告)号：US20180166294A1

公开(公告)日：2018-06-14

申请号：US15377635

申请日：2016-12-13

Applicant: Intel Corporation

Inventor： Zheng Zhou ,  Yi Li ,  Tao Wu ,  Nikhil Sharma

IPC: H01L21/3105 ,  H01L21/683 ,  H01L21/56 ,  H05B3/22

CPC classification number: H05B3/22 ,  H01L21/31058 ,  H01L21/4846 ,  H01L23/498 ,  H01L2021/607 ,  H05B2203/033

Abstract: Embodiments herein relate to methods and apparatus to achieve substantially uniform package thickness after forming a buildup layer on a package substrate of an integrated circuit. Some embodiments include applying a resin to the buildup layer to form a resin layer on top of at least a portion of the buildup layer and substantially evening out the surface formed by the resin layer. Some embodiments include vibrating a hot press onto the top surface of the buildup layer and vibrating the hot press in an ultrasonic and/or a scrubbing motion. Other embodiments may be described and/or claimed.

公开(公告)号：US09741606B2

公开(公告)日：2017-08-22

申请号：US14821647

申请日：2015-08-07

Applicant: INTEL CORPORATION

Inventor： Zheng Zhou ,  Amanda E. Schuckman ,  Sri Ranga Sai Boyapati

IPC: H01L23/498 ,  H01L21/768 ,  H01L23/14 ,  H01L21/48

CPC classification number: H01L21/76814 ,  H01L21/486 ,  H01L21/76804 ,  H01L21/76816 ,  H01L21/76879 ,  H01L23/145 ,  H01L23/49822 ,  H01L23/49827

Abstract: Embodiments herein may relate to a technique for generating a via in a substrate. Specifically, the technique may include coupling a polyethylene terephthalate (PET) layer, a protective metal layer, and a build-up layer to a metal layer. The process may further include etching a via in the PET layer, the protective metal layer, and at least a portion of the build-up layer. The process may further include performing a plasma desmear process on the substrate and then peeling the PET layer to remove the PET layer and the protective metal layer. Other embodiments may be described and/or claimed.

公开(公告)号：US09917044B2

公开(公告)日：2018-03-13

申请号：US15028278

申请日：2015-05-13

Applicant: INTEL CORPORATION

Inventor： Zheng Zhou ,  Mihir K. Roy ,  Chong Zhang ,  Kyu-Oh Lee ,  Amanda E. Schuckman

IPC: H01L23/52 ,  H01L23/498 ,  H01L23/00 ,  H01L21/768

CPC classification number: H01L23/49827 ,  H01L21/76804 ,  H01L21/76879 ,  H01L23/145 ,  H01L23/49838 ,  H01L23/66 ,  H01L24/14 ,  H01L2223/6616 ,  H01L2223/6677 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/15311

Abstract: Some embodiments of the present disclosure describe a multi-layer package with a bi-layered dielectric structure and associated techniques and configurations. In one embodiment, an integrated circuit (IC) package assembly includes a dielectric structure coupled with a metal layer, with the dielectric structure including a first dielectric layer and a second dielectric layer, wherein the first dielectric layer has a thickness less than a thickness of the second dielectric layer and a dielectric loss tangent greater than a dielectric loss tangent of the second layer. Other embodiments may be described and/or claimed.

公开(公告)号：US20160280535A1

公开(公告)日：2016-09-29

申请号：US14671549

申请日：2015-03-27

Applicant: Intel Corporation

Inventor： Kyu Oh Lee ,  Zheng Zhou ,  Islam A. Salama ,  Feras Eid ,  Sasha N. Oster ,  Lay Wai Kong ,  Javier Soto Gonzalez

IPC: B81B3/00 ,  B81C1/00

CPC classification number: B81B7/0077 ,  B81C2203/0109

Abstract: Methods of forming sensor integrated package devices and structures formed thereby are described. An embodiment includes providing a substrate core, wherein a first conductive trace structure and a second conductive trace structure are disposed on the substrate core, forming a cavity between the first conductive trace structure and the second conductive trace structure, and placing a magnet on a resist material disposed on a portion of each of the first and second conductive trace structures, wherein the resist material does not extend over the cavity.

Abstract translation: 描述形成传感器集成封装器件和由此形成的结构的方法。 一个实施例包括提供衬底芯，其中第一导电迹线结构和第二导电迹线结构设置在衬底芯上，在第一导电迹线结构和第二导电迹线结构之间形成空腔，并将磁体放置在抗蚀剂上 设置在第一和第二导电迹线结构中的每一个的一部分上的材料，其中抗蚀剂材料不在空腔上延伸。