公开(公告)号：US09832011B1

公开(公告)日：2017-11-28

申请号：US15198115

申请日：2016-06-30

Applicant: Intel IP Corporation

Inventor： Christian Wicpalek ,  Tobias Buckel ,  Andreas Menkhoff

IPC: H04L7/033 ,  H04L12/26 ,  H04L12/24 ,  H03C3/09 ,  H03L7/193 ,  H03L7/10 ,  H03L7/099 ,  H03L7/085 ,  H03L7/18 ,  H03L7/113 ,  H03L7/081 ,  H03L7/093 ,  H03L7/197 ,  H03L7/107 ,  H03L7/183 ,  H03L7/091 ,  H03L7/08 ,  H03L7/089 ,  H03L7/087 ,  H03C3/20

CPC classification number: H04L7/033 ,  H03C3/0916 ,  H03C3/0925 ,  H03C3/0933 ,  H03C3/0941 ,  H03C3/095 ,  H03C3/0958 ,  H03C3/0966 ,  H03C3/0991 ,  H03C3/20 ,  H03L7/08 ,  H03L7/0802 ,  H03L7/081 ,  H03L7/085 ,  H03L7/087 ,  H03L7/089 ,  H03L7/0891 ,  H03L7/091 ,  H03L7/093 ,  H03L7/099 ,  H03L7/0995 ,  H03L7/104 ,  H03L7/1075 ,  H03L7/113 ,  H03L7/18 ,  H03L7/183 ,  H03L7/193 ,  H03L7/1976 ,  H03L2207/06 ,  H03L2207/50 ,  H04L41/0681 ,  H04L43/028

Abstract: Performance indicator circuitry is provided for characterizing performance of a phase locked loop (PLL) in a phase path of a polar modulator or polar transmitter that is used to generate a phase modulated RF signal. The PLL includes an oscillator, a high pass path, and a low pass path. The low pass path includes a loop filter. The performance indicator circuitry includes first input circuitry and parameter calculation circuitry. The first input circuitry is configured to input a loop filter signal from the loop filter. The parameter calculation circuitry is configured to compute a value for a performance indicator based on the loop filter signal and control or characterize an aspect of operation of the PLL based on the value.