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    Method of planarizing thin film layers deposited over a common circuit base
    1.
    发明授权
    Method of planarizing thin film layers deposited over a common circuit base 失效
    在公共电路基底上沉积薄膜层的平面化方法

    公开(公告)号：US6165892A

    公开(公告)日：2000-12-26

    申请号：US127580

    申请日：1998-07-31

    申请人： David J. Chazan ,  Ted T. Chen ,  Todd S. Kaplan ,  James L. Lykins ,  Michael P. Skinner ,  Jan I. Strandberg

    发明人： David J. Chazan ,  Ted T. Chen ,  Todd S. Kaplan ,  James L. Lykins ,  Michael P. Skinner ,  Jan I. Strandberg

    IPC分类号： H01L21/48 ,  H01L23/538 ,  H05K1/02 ,  H05K3/00 ,  H05K3/46 ,  H01L21/4763

    CPC分类号： H05K3/4673 ,  H01L21/481 ,  H01L21/4857 ,  H01L23/5383 ,  H01L23/5385 ,  H01L2924/0002 ,  H01L2924/3011 ,  H05K1/0271 ,  H05K3/0023 ,  H05K3/0032 ,  H05K3/4602 ,  H05K3/4644 ,  H05K2201/0195 ,  H05K2201/068 ,  H05K2201/09536 ,  H05K2201/0959 ,  H05K2201/09881 ,  H05K2203/0585 ,  H05K2203/0759 ,  H05K2203/1476 ,  H01L2924/00

    摘要： A method for forming a planarized thin film dielectric film on a surface of a common circuit base upon which one or more integrated circuits are to be attached. The common circuit base includes raised features formed over its surface such that the raised features define a trench area between them. The method includes the steps of forming a first layer of the dielectric film over the common circuit base and over the raised features and the trench, then patterning the newly formed layer to remove portions of the layer formed over the raised features and expose the raised features. After the layer is patterned, formation of the dielectric film is completed by forming a second layer of the dielectric film over the patterned first layer. Additional film deposition and film patterning steps are performed to complete the layout of a thin film interconnect structure over said common circuit base, and an integrated circuit die is attached to the common circuit base and electrically connecting to the thin film interconnect structure. In a preferred embodiment, the first and second layers of the dielectric film are both formed from a photo-definable material and the patterning step includes exposing the first layer to light through a patterned mask corresponding to the raised features and developing the exposed layer with a developing solution to etch away portions of the first layer formed over the raised features.

    摘要翻译： 一种用于在公共电路基底的表面上形成平坦化的薄膜电介质膜的方法，一个或多个集成电路将安装在该公共电路基底上。 公共电路基座包括在其表面上形成的凸起特征，使得凸起特征在它们之间限定沟槽区域。 该方法包括以下步骤：在公共电路基底上方和凸起的特征​​和沟槽上形成电介质膜的第一层，然后对新形成的层进行图案化以去除在凸起特征上形成的层的部分，并暴露凸起特征 。 在层被图案化之后，通过在图案化的第一层上形成电介质膜的第二层来完成电介质膜的形成。 执行附加的膜沉积和膜图案化步骤以在所述公共电路基底上完成薄膜互连结构的布局，并且集成电路管芯附接到公共电路基座并电连接到薄膜互连结构。 在优选实施例中，电介质膜的第一和第二层都由光可定义材料形成，并且图案化步骤包括通过对应于凸起特征的图案化掩模将第一层暴露于光，并将曝光层用 显影溶液以蚀刻形成在凸起特征上的第一层的部分。

    Trace gas sensor with reduced degradation
    4.
    发明授权
    Trace gas sensor with reduced degradation 有权
    痕量气体传感器降低降解

    公开(公告)号：US07278291B2

    公开(公告)日：2007-10-09

    申请号：US11348925

    申请日：2006-02-06

    申请人： David J. Chazan ,  David J. Anvar ,  Autumn Talbott

    发明人： David J. Chazan ,  David J. Anvar ,  Autumn Talbott

    IPC分类号： G01N7/00 ,  G01N9/00

    CPC分类号： G01N33/497

    摘要： The degradation over time that is commonly seen with analyte-binding proteins when used as sensors for trace amounts of an analyte in a gaseous mixture is reduced by maintaining the sensor in a low-oxygen or oxygen-free environment.

    摘要翻译： 当用作气体混合物中微量分析物的传感器时，通过分析物结合蛋白通常观察到的随时间的降解通过将传感器保持在低氧或无氧环境中来降低。

    Method and structure for detecting open vias in high density interconnect substrates
    5.
    发明授权
    Method and structure for detecting open vias in high density interconnect substrates 失效
    用于检测高密度互连基板中的开孔的方法和结构

    公开(公告)号：US06262579B1

    公开(公告)日：2001-07-17

    申请号：US09191594

    申请日：1998-11-13

    申请人： David J. Chazan ,  James L. Lykins

    发明人： David J. Chazan ,  James L. Lykins

    IPC分类号： H01H3102

    CPC分类号： H01L21/4857 ,  B23K26/382 ,  B23K26/40 ,  B23K2103/12 ,  B23K2103/172 ,  B23K2103/42 ,  B23K2103/50 ,  H01L23/5383 ,  H01L23/5385 ,  H01L2924/0002 ,  H01L2924/3011 ,  H05K1/0266 ,  H05K3/241 ,  H05K3/244 ,  H05K3/4602 ,  H05K2203/162 ,  H01L2924/00

    摘要： A method for testing for open circuits on a common circuit base having pads for making electrical contact to the common circuit base on both the top and bottom of the circuit base. The common circuit base includes a thin film metal interconnect structure formed on its upper surface and the thin film interconnect structure including an upper dielectric layer deposited over a thin film metalization layer that has contact openings etched through the dielectric layer at selected locations for the formation of contact pads. The method includes the steps of (1) forming a seed layer over the upper dielectric layer and over the contact openings; (2) forming a photoresist layer over the seed layer and patterning the photoresist layer to expose selected portions of the seed layer such that the selected portions correspond generally to the contact openings; (3) plating a conductive layer over the patterned seed layer to form plated contact pads that are electrically connected to an underlying thin film metalization layer; and (4) inspecting the plated conductive layer for open circuits prior to performing subsequent process steps and/or tests. In different embodiments, such subsequent process steps and/or tests include: stripping the photoresist in areas where the contact pads are not formed to expose the seed layer underlying the photoresist; removing the exposed seed layer and performing an electrical test on the common circuit base to determine if any short circuits exist in the interconnect structure.

    摘要翻译： 一种用于在公共电路基座上测试开路的方法，该公共电路基座具有用于在电路基座的顶部和底部上与公共电路基座进行电接触的焊盘。 公共电路基底包括在其上表面上形成的薄膜金属互连结构，薄膜互连结构包括沉积在薄膜金属化层上的上电介质层，该介电层在选定的位置处具有通过介电层蚀刻的接触开口，用于形成 接触垫 该方法包括以下步骤：（1）在上电介质层上方和接触开口上形成晶种层; （2）在晶种层上形成光致抗蚀剂层，并且对所述光致抗蚀剂层进行构图以暴露所述种子层的选定部分，使得所选择的部分大致对应于所述接触开口; （3）在图案化种子层上镀覆导电层以形成电连接到下面的薄膜金属化层的电镀接触焊盘; 以及（4）在执行后续处理步骤和/或测试之前检查镀覆的导电层以用于开路。 在不同的实施例中，这样的后续工艺步骤和/或测试包括：在不形成接触焊盘以暴露光致抗蚀剂下面的种子层的区域中剥离光致抗蚀剂; 去除暴露的种子层并在公共电路基底上执行电测试以确定互连结构中是否存在短路。

    Reduction of carbon monoxide interference in gaseous analyte detectors
    7.
    发明授权
    Reduction of carbon monoxide interference in gaseous analyte detectors 有权
    降低气态分析物检测器中的一氧化碳干扰

    公开(公告)号：US07611671B2

    公开(公告)日：2009-11-03

    申请号：US11250958

    申请日：2005-10-14

    申请人： David J. Anvar ,  David J. Chazan ,  Bryan P. Flaherty ,  Bhairavi R. Parikh

    发明人： David J. Anvar ,  David J. Chazan ,  Bryan P. Flaherty ,  Bhairavi R. Parikh

    IPC分类号： G01N33/497

    CPC分类号： G01N21/783 ,  G01N21/76 ,  G01N33/0037 ,  G01N33/0059 ,  G01N2021/7773 ,  G01N2021/7783 ,  G01N2021/7786 ,  Y02A50/245 ,  Y10T436/177692 ,  Y10T436/179228

    摘要： Highly sensitive devices for detecting nitric oxide and/or other gaseous analytes in gaseous samples are improved by the incorporation of a carbon monoxide scavenger in the interior of the device or in the device packaging. The release of carbon monoxide within the housing of the device by the plastic used in the construction of the housing or by anything within the device that releases carbon monoxide causes a loss in sensitivity due to competition between the carbon monoxide and the nitric oxide for the binding sites on the device sensor. The scavenger corrects this by either catalyzing the oxidation of carbon monoxide to the less competitive carbon dioxide or immobilizing the carbon monoxide by affinity-type or covalent binding. Analogous effects are achieved for analytes other than nitric oxide but that likewise encounter interference from carbon monoxide in binding to sensors.

    摘要翻译： 通过将一氧化碳清除剂并入装置的内部或在装置包装中，用于检测气态样品中一氧化氮和/或其它气态分析物的高灵敏度装置得到改善。 通过用于建筑外壳中的塑料或释放一氧化碳的装置内的任何物质，在装置的壳体内释放一氧化碳导致由于一氧化碳和一氧化氮之间的竞争导致的结合的灵敏度损失 设备传感器上的站点。 清除剂通过催化一氧化碳氧化成竞争力较低的二氧化碳或通过亲和型或共价结合固定一氧化​​碳来纠正这一点。 对一氧化氮以外的分析物也能达到类似的效果，但同样遇到一氧化碳与传感器结合的干扰。