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    Thin interface pellicle for dense arrays of electrical interconnects
    2.
    发明授权
    Thin interface pellicle for dense arrays of electrical interconnects 失效
    用于密集电气互连阵列的薄接口防护薄膜

    公开(公告)号：US5207585A

    公开(公告)日：1993-05-04

    申请号：US606413

    申请日：1990-10-31

    申请人： Herbert P. Byrnes ,  Jean-Marc Halbout ,  Michael R. Scheuermann ,  Eugene Shapiro

    发明人： Herbert P. Byrnes ,  Jean-Marc Halbout ,  Michael R. Scheuermann ,  Eugene Shapiro

    IPC分类号： G01R31/26 ,  G01R1/067 ,  G01R1/073 ,  H01L21/312 ,  H01L21/60 ,  H01L21/66 ,  H01R12/62 ,  H01R12/71 ,  H05K3/36

    CPC分类号： H01R12/62 ,  G01R1/06711 ,  G01R1/0735 ,  H01R12/714 ,  H05K3/365 ,  H01L2924/0002 ,  H01R2201/20

    摘要： A thin interface pellicle probe for making temporary or permanent interconnections to pads or bumps on a semiconductor device wherein the pads or bumps may be arranged in high density patterns is described incorporating an electrode for each pad or bump wherein the electrode has a raised portion thereon for penetrating the surface of the pad or bump to create sidewalls to provide a clean contact surface and the electrode has a recessed surface to limit the penetration of the raised portion. The electrodes may be affixed to a thin flexible membrane to permit each contact to have independent movement over a limited distance and of a limited rotation. The invention overcomes the problem of making easily breakable electrical interconnections to high density arrays of pads or bumps on integrated circuit structures for testing, burn-in or package interconnect and testing applications.

    摘要翻译： 描述了用于对半导体器件上的焊盘或凸起进行临时或永久互连的薄接口防护薄膜探针，其中焊盘或凸块可以以高密度图案布置，其中包括用于每个焊盘或凸块的电极，其中电极在其上具有凸起部分， 穿过垫或凸块的表面以产生侧壁以提供清洁的接触表面，并且电极具有凹陷表面以限制凸起部分的穿透。 电极可以固定到薄的柔性膜上，以允许每个接触件在有限的距离和有限的旋转上具有独立的运动。 本发明克服了在用于测试，老化或封装互连和测试应用的集成电路结构上制造易于断开的电互连到高密度阵列的焊盘或凸块的问题。

    High speed silicon-based lateral junction photodetectors having recessed electrodes and thick oxide to reduce fringing fields
    3.
    发明授权
    High speed silicon-based lateral junction photodetectors having recessed electrodes and thick oxide to reduce fringing fields 失效
    具有凹陷电极和厚氧化物的高速硅基侧面光电探测器，以减少边缘场

    公开(公告)号：US5525828A

    公开(公告)日：1996-06-11

    申请号：US294897

    申请日：1994-08-23

    申请人： Ernest Bassous ,  Jean-Marc Halbout ,  Subramanian S. Iyer ,  Rajiv V. Joshi ,  Vijay P. Kesan ,  Michael R. Scheuermann ,  Massimo A. Ghioni

    发明人： Ernest Bassous ,  Jean-Marc Halbout ,  Subramanian S. Iyer ,  Rajiv V. Joshi ,  Vijay P. Kesan ,  Michael R. Scheuermann ,  Massimo A. Ghioni

    IPC分类号： H01L31/02 ,  H01L31/105 ,  H01L31/108 ,  H01L31/07

    CPC分类号： H01L31/105 ,  H01L31/02024 ,  H01L31/1085

    摘要： Silicon-VLSI-compatible photodetectors, in the form of a metal-semiconductor-metal photodetector (MSM-PD) or a lateral p-i-n photodetector (LPIN-PD), are disclosed embodying interdigitated metallic electrodes on a silicon surface. The electrodes of the MSM-PD have a moderate to high electron and hole barrier height to silicon, for forming the Schottky barriers, and are fabricated so as to be recessed in the surface semiconducting layer of silicon through the use of self-aligned metallization either by selective deposition or by selective reaction and etching, in a manner similar to the SALICIDE concept. Fabrication is begun by coating the exposed Si surface of a substrate with a transparent oxide film, such that the Si/oxide interface exhibits low surface recombination velocity. The interdigitated pattern is then etched through the oxide film by lithography to expose the Si surface and metallic electrode members are formed selectively in the exposed Si surface, using self-aligned metallization to produce thin interdigitated electrodes recessed below the silicon surface, which itself may be on a comparatively thin Si layer. The electrodes may be spaced to minimize the interdigital carrier transit time and maximize the sensitivity and the entire process and structure are compatible with conventional silicon integrated circuit (IC) technology. A further feature involves isolating the semiconductor surface layer from the substrate by a layer that may be either 1) transparent and insulating, 2) optically absorbing, or 3) optically reflecting, so that the photocarriers recombine before they can be collected by the field. In the latter case, the photodetector acts as a resonant cavity, resulting in an increase in the number of carriers that are generated, and hence a more sensitive device.

    摘要翻译： 在硅表面上公开了金属 - 半导体 - 金属光电探测器（MSM-PD）或横向p-i-n光电检测器（LPIN-PD）形式的硅 - VLSI兼容光电探测器。 MSM-PD的电极具有对于硅的中等到高电子和空穴阻挡高度，用于形成肖特基势垒，并且通过使用自对准金属化制造成凹入硅的表面半导体层 通过选择性沉积或通过选择性反应和蚀刻，以类似于SALICIDE概念的方式。 通过用透明氧化膜涂覆衬底的暴露的Si表面开始制造，使得Si /氧化物界面表现出低的表面复合速度。 然后通过光刻法将交错图案通过氧化膜蚀刻以暴露Si表面，并且使用自对准金属化选择性地在暴露的Si表面中形成金属电极构件，以产生凹陷在硅表面下方的薄的叉指电极，其本身可以是 在较薄的Si层上。 这些电极可以间隔开，以最小化叉指运送通过时间并使灵敏度最大化，并且整个过程和结构与传统的硅集成电路（IC）技术相兼容。 另一个特征包括通过可以是1）透明和绝缘，2）光学吸收或3）光学反射的层将衬底的半导体表面层隔离，使得光载流子在它们可以被场收集之前复合。 在后一种情况下，光电探测器用作谐振腔，导致所产生的载流子数量增加，因此增加了更敏感的装置。

    3D inter-stratum connectivity robustness
    4.
    发明授权
    3D inter-stratum connectivity robustness 有权
    3D层间连通性鲁棒性

    公开(公告)号：US08381156B1

    公开(公告)日：2013-02-19

    申请号：US13217381

    申请日：2011-08-25

    申请人： Michael P. Beakes ,  Shih-Hsien Lo ,  Michael R. Scheuermann ,  Matthew R. Wordeman

    发明人： Michael P. Beakes ,  Shih-Hsien Lo ,  Michael R. Scheuermann ,  Matthew R. Wordeman

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5081 ,  G06F2217/40 ,  H01L25/0657 ,  H01L2924/0002 ,  H01L2924/00

    摘要： There is provided a method for verifying inter-stratum connectivity for two or more strata to be combined into a 3D chip stack. Each of the two or more strata has 3D elements including active 3D elements, mechanical 3D elements, and dummy 3D elements. The method includes performing a respective 2D layout versus schematic verification on each of the two or more strata with respect to at least the 3D elements to pre-ensure an absence of shorts between the 3D elements when the two or more strata are subsequently stacked into the 3D chip stack. The method further includes checking inter-stratum interconnectivity between each adjacent pair of strata in the 3D chip stack.

    摘要翻译： 提供了一种用于验证要组合成3D芯片堆栈的两个或更多个层的层间连通性的方法。 两个或更多个层中的每一个具有包括主动3D元素，机械3D元素和虚拟3D元素的3D元素。 该方法包括相对于至少3D元件在两个或更多个层中的每一个上执行相应的2D布局，以相对于示意图验证，以便当两个或更多个层随后被堆叠到3D元素中时，预先确保在3D元件之间不存在短路 3D芯片堆栈。 该方法还包括检查3D芯片堆叠中每个相邻层之间的层间互连性。

    Vertical power budgeting and shifting for three-dimensional integration
    5.
    发明授权
    Vertical power budgeting and shifting for three-dimensional integration 有权
    垂直功率预算和三维一体化转移

    公开(公告)号：US08516426B2

    公开(公告)日：2013-08-20

    申请号：US13217429

    申请日：2011-08-25

    申请人： Pradip Bose ,  Gary D. Carpenter ,  Michael S. Floyd ,  Eren Kursun ,  Phillip J. Restle ,  Michael R. Scheuermann

    发明人： Pradip Bose ,  Gary D. Carpenter ,  Michael S. Floyd ,  Eren Kursun ,  Phillip J. Restle ,  Michael R. Scheuermann

    IPC分类号： G06F17/50 ,  G06F9/455 ,  G06F11/22

    CPC分类号： H01L23/50 ,  G06F17/5045 ,  G06F2217/78 ,  H01L25/0657 ,  H01L2224/16145 ,  H01L2225/06513 ,  H01L2225/06544 ,  H01L2225/06565

    摘要： A method is provided for managing power distribution on a three-dimensional chip stack having two or more strata, a plurality of vertical power delivery structures, and multiple stack components. At least two stack components are on different strata. Operating modes are stored that respectively have different power dissipations. A respective effective power budget is determined for each of the at least two stack components based on respective ones of the operating modes targeted therefor, and power characteristics and thermal characteristics of at least some of the stack components inclusive or exclusive of the at least two stack components. The respective ones of the plurality of operating modes targeted for the at least two stack components are selectively accepted or re-allocated based on the respective effective power budget for each of the at least two stack components, power constraints, and thermal constraints. The power constraints include vertical structure electrical constraints.

    摘要翻译： 提供了一种用于管理具有两个或更多个层，多个垂直功率传递结构和多个堆叠组件的三维芯片堆叠上的功率分配的方法。 至少两个堆叠组件位于不同的层。 存储分别具有不同功耗的工作模式。 基于针对其的各个操作模式确定所述至少两个堆叠组件中的每一个的相应的有效功率预算，以及包括或排除所述至少两个堆叠的至少一些堆叠组件的功率特性和热特性 组件。 基于用于至少两个堆叠组件中的每一个，功率约束和热约束的相应的有效功率预算来选择性地接受或重新分配针对至少两个堆叠组件的多个操作模式中的各个操作模式。 功率约束包括垂直结构电气约束。

    Hindering Side-Channel Attacks in Integrated Circuits
    6.
    发明申请
    Hindering Side-Channel Attacks in Integrated Circuits 审中-公开
    在集成电路中受阻的侧向通道攻击

    公开(公告)号：US20120124669A1

    公开(公告)日：2012-05-17

    申请号：US12945155

    申请日：2010-11-12

    申请人： Gary D. Carpenter ,  Eren Kursun ,  Phillip J. Restle ,  Michael R. Scheuermann

    发明人： Gary D. Carpenter ,  Eren Kursun ,  Phillip J. Restle ,  Michael R. Scheuermann

    IPC分类号： G06F21/00

    CPC分类号： G06F21/86 ,  G06F21/71 ,  G06F21/755

    摘要： A mechanism is provided for protecting a layer of functional units from side-channel attacks. A determination is made as to whether one or more subsets of functional units in a set of functional units in the layer of functional units is performing operations of a critical nature. Responsive to a determination that there is one or more subsets of functional units that are performing the operations of the critical nature, at least one concealing pattern is generated in a concealing layer in order to conceal the operations of the critical nature being performed by each of the subset of functional units. The concealing layer is electrically and physically coupled to the layer of functional units.

    摘要翻译： 提供了用于保护功能单元层免受侧信道攻击的机制。 确定功能单元层中的一组功能单元中的一个或多个功能单元的子集是否执行关键性质的操作。 响应于确定存在正在执行关键性质的操作的功能单元的一个或多个子集，在隐藏层中生成至少一个隐藏模式，以便隐藏正在执行的关键性质的操作 功能单元的子集。 隐藏层电性和物理耦合到功能单元层。

    Process for managing complex pre-wired net segments in a VLSI design
    7.
    发明授权
    Process for managing complex pre-wired net segments in a VLSI design 有权
    在VLSI设计中管理复杂的预先有线网段的过程

    公开(公告)号：US07681169B2

    公开(公告)日：2010-03-16

    申请号：US11846577

    申请日：2007-08-29

    申请人： Christopher J. Berry ,  Michael A. Bowen ,  Michael R. Scheuermann ,  Michael H. Wood

    发明人： Christopher J. Berry ,  Michael A. Bowen ,  Michael R. Scheuermann ,  Michael H. Wood

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5077

    摘要： A method for pre-wiring through multiple levels of metal using flues includes steps of: receiving information comprising flue geometries and flue properties; producing multiple routing patterns of a design for the flues; identifying macro instance terminals to be pre-wired in the design; selecting at least one of the routing patterns for the macro instance terminals in the design to avoid blockage; and instantiating the design such that the flues can be manipulated as vias.

    摘要翻译： 使用烟道预先接线多层金属的方法包括以下步骤：接收包括烟道几何形状和烟道特性的信息; 生成针对流感的设计的多个路由模式; 识别要在设计中预先布线的宏实例终端; 在设计中选择用于宏实例终端的路由模式中的至少一个以避免阻塞; 并实例化设计，使得烟道可以被操纵为过孔。

    Process for Managing Complex Pre-Wired Net Segments in a VLSI Design
    10.
    发明申请
    Process for Managing Complex Pre-Wired Net Segments in a VLSI Design 有权
    在VLSI设计中管理复杂的预先有线网段的过程

    公开(公告)号：US20090064081A1

    公开(公告)日：2009-03-05

    申请号：US11846577

    申请日：2007-08-29

    申请人： Christopher J. Berry ,  Michael A. Bowen ,  Michael R. Scheuermann ,  Michael H. Wood

    发明人： Christopher J. Berry ,  Michael A. Bowen ,  Michael R. Scheuermann ,  Michael H. Wood

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5077

    摘要： A method for pre-wiring through multiple levels of metal using flues includes steps of: receiving information comprising flue geometries and flue properties; producing multiple routing patterns of a design for the flues; identifying macro instance terminals to be pre-wired in the design; selecting at least one of the routing patterns for the macro instance terminals in the design to avoid blockage; and instantiating the design such that the flues can be manipulated as vias.

    摘要翻译： 使用烟道预先接线多层金属的方法包括以下步骤：接收包括烟道几何形状和烟道特性的信息; 生成针对流感的设计的多个路由模式; 识别要在设计中预先布线的宏实例终端; 在设计中选择用于宏实例终端的路由模式中的至少一个以避免阻塞; 并实例化设计，使得烟道可以被操纵为过孔。