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    Methods for fabricating FinFET integrated circuits in bulk semiconductor substrates
    5.
    发明授权
    Methods for fabricating FinFET integrated circuits in bulk semiconductor substrates 有权
    在半导体衬底中制造FinFET集成电路的方法

    公开(公告)号：US08461008B2

    公开(公告)日：2013-06-11

    申请号：US13210086

    申请日：2011-08-15

    Applicant: Jin Cho

    Inventor： Jin Cho

    IPC: H01L21/336

    CPC classification number: H01L21/823431 ,  H01L21/76224 ,  H01L29/66545

    Abstract: Methods are provided for fabricating FinFETs that avoid thickness uniformity problems across a die or a substrate. One method includes providing a semiconductor substrate divided into a plurality of chips, each chip bounded by scribe lines. The substrate is etched to form a plurality of fins, each of the fins extending uniformly across the width of the chips. An oxide is deposited to fill between the fins and is etched to recess the top of the oxide below the top of the fins. An isolation hard mask is deposited and patterned overlying the plurality of fins and is used as an etch mask to etch trenches in the substrate defining a plurality of active areas, each of the plurality of active areas including at least a portion of at least one of the fins. The trenches are filled with an insulating material to isolate between adjacent active areas.

    Abstract translation: 提供了用于制造FinFET的方法，其避免了晶片或衬底上的厚度均匀性问题。 一种方法包括提供划分成多个芯片的半导体衬底，每个芯片由划线限定。 蚀刻基板以形成多个翅片，每个翅片均匀地延伸穿过芯片的宽度。 沉积氧化物以填充在翅片之间并且被蚀刻以使在该翅片顶部下方的氧化物的顶部凹陷。 隔离硬掩模被沉积并且图案覆盖在多个翅片上，并且被用作蚀刻掩模以蚀刻限定多个有效区域的衬底中的沟槽，所述多个有效区域中的每一个包括至少一部分至少一个 翅片 沟槽填充绝缘材料以隔离相邻的活性区域。

    MEMORY DEVICE AND METHOD THEREOF
    6.
    发明申请
    MEMORY DEVICE AND METHOD THEREOF 有权
    存储器件及其方法

    公开(公告)号：US20100146330A1

    公开(公告)日：2010-06-10

    申请号：US12330012

    申请日：2008-12-08

    Applicant: Sang Dhong ,  Jin Cho ,  John Wuu ,  Gurupada Mandal

    Inventor： Sang Dhong ,  Jin Cho ,  John Wuu ,  Gurupada Mandal

    IPC: G06F11/20

    CPC classification number: G06F11/1048 ,  G11C2029/0411

    Abstract: An error correction module is disclosed whereby two bit cells are used to store a bit of information in a redundant manner so that a redundant error correction module can correct a sporadic data error at one of the two bits.

    Abstract translation: 公开了一种误差校正模块，其中两个比特单元用于以冗余的方式存储一位信息，使得冗余纠错模块可以校正两个比特之一的零星数据错误。

    Server system for performing communication over wireless network and communication method thereof
    8.
    发明申请
    Server system for performing communication over wireless network and communication method thereof 有权
    用于通过无线网络进行通信的服务器系统及其通信方法

    公开(公告)号：US20050125713A1

    公开(公告)日：2005-06-09

    申请号：US10896848

    申请日：2004-07-23

    Applicant: Young Roh ,  Jung Kim ,  Jin Cho ,  Jae Chang ,  Sang Kang ,  Sang Kim ,  Pan Kim ,  Kwang Hong

    Inventor： Young Roh ,  Jung Kim ,  Jin Cho ,  Jae Chang ,  Sang Kang ,  Sang Kim ,  Pan Kim ,  Kwang Hong

    IPC: H04L12/26 ,  G08C25/02 ,  H04L1/00 ,  H04L1/08 ,  H04L1/18 ,  H04L12/00 ,  H04Q7/30

    CPC classification number: H04L1/18 ,  H04L1/0002

    Abstract: Disclosed are a server system for performing communication over a wireless network and a communication method thereof. The server system comprises at least one client device and a server device for performing a state monitoring operation or a control operation for the client device over the wireless network. When a data packet is sent, the server device begins to send a following packet by variably applying a transmission rate according to a network transmission state when a leading packet has been completely transmitted. Because a transmission rate can be set appropriately to the network state, the number of unnecessary retransmissions can be reduced. Therefore, transmission delay can be avoided and stable and rapid wireless communication can be achieved.

    Abstract translation: 公开了一种通过无线网络进行通信的服务器系统及其通信方法。 服务器系统包括至少一个客户端设备和服务器设备，用于通过无线网络对客户端设备执行状态监视操作或控制操作。 当发送数据分组时，当前导分组被完全发送时，服务器设备开始通过可变地应用根据网络传输状态的传输速率发送后续分组。 因为可以适当地设置传输速率到网络状态，所以可以减少不必要的重发次数。 因此，可以避免传输延迟，实现稳定快速的无线通信。

    Methods of forming a dielectric cap layer on a metal gate structure
    10.
    发明授权
    Methods of forming a dielectric cap layer on a metal gate structure 有权
    在金属栅极结构上形成电介质盖层的方法

    公开(公告)号：US09117877B2

    公开(公告)日：2015-08-25

    申请号：US13350908

    申请日：2012-01-16

    Applicant: Xiuyu Cai ,  Ruilong Xie ,  Jin Cho ,  John Iacoponi

    Inventor： Xiuyu Cai ,  Ruilong Xie ,  Jin Cho ,  John Iacoponi

    IPC: H01L21/311 ,  H01L21/762 ,  H01L29/78 ,  H01L29/66

    CPC classification number: H01L29/785 ,  H01L21/76232 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/66795

    Abstract: Disclosed herein are various methods of forming isolation structures on FinFETs and other semiconductor devices, and the resulting devices that have such isolation structures. In one example, the method includes forming a plurality of spaced-apart trenches in a semiconducting substrate, wherein the trenches define a fin for a FinFET device, forming a layer of insulating material in the trenches, wherein the layer of insulating material covers a lower portion of the fin but not an upper portion of the fin, forming a protective material on the upper portion of the fin, and performing a heating process in an oxidizing ambient to form a thermal oxide region on the covered lower portion of the fin.

    Abstract translation: 本文公开了在FinFET和其它半导体器件上形成隔离结构的各种方法，以及具有这种隔离结构的所得器件。 在一个示例中，该方法包括在半导体衬底中形成多个间隔开的沟槽，其中沟槽限定用于FinFET器件的鳍片，在沟槽中形成绝缘材料层，其中绝缘材料层覆盖下部 翅片的一部分而不是翅片的上部，在翅片的上部形成保护材料，并且在氧化环境中进行加热处理，以在翅片的被覆盖的下部形成热氧化物区域。

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