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    Wafer level package of image sensor and method for manufacturing the same
    1.
    发明申请
    Wafer level package of image sensor and method for manufacturing the same 审中-公开
    图像传感器的晶片级封装及其制造方法

    公开(公告)号：US20080296714A1

    公开(公告)日：2008-12-04

    申请号：US12155267

    申请日：2008-05-30

    申请人： Jingli Yuan ,  Won Kvu Jeung ,  Dae Jun Kim ,  Chang Hyun Lim ,  Young Do Kweon ,  Jae Cheon Doh

    发明人： Jingli Yuan ,  Won Kvu Jeung ,  Dae Jun Kim ,  Chang Hyun Lim ,  Young Do Kweon ,  Jae Cheon Doh

    IPC分类号： H01L31/0232 ,  H01L31/18

    CPC分类号： H01L27/14618 ,  H01L27/14632 ,  H01L27/14687 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2924/16195 ,  H01L2924/3025 ,  H01L2924/00014 ,  H01L2924/00

    摘要： Provided is a wafer level package of an image sensor capable of simply and easily packaging an image sensor in a packaging process, and a method for manufacturing the same. The wafer level package of an image sensor includes a lower substrate including an image sensor, a conductive pattern coupled to the image sensor, and a plurality of vias coupled to the conductive pattern; a micro lens array film having a plurality of micro lenses corresponding to the image sensor, the micro lenses being formed on the lower substrate; and a sealing line surrounding the image sensor while being spaced apart from the image sensor and being in contact with an upper substrate. The wafer level package may be useful to have an electrical connection structure using vias without any need to a bonding wire, an electrode pad and an electrode lead in the conventional wafer level package since a packaging process is carried out by bonding a wafer for an upper substrate with a plurality of the vias being provided in a wafer for a lower substrate

    摘要翻译： 提供了能够简单且容易地在封装过程中封装图像传感器的图像传感器的晶片级封装及其制造方法。 图像传感器的晶片级封装包括下基板，其包括图像传感器，耦合到图像传感器的导电图案以及耦合到导电图案的多个通孔; 具有与所述图像传感器对应的多个微透镜的微透镜阵列膜，所述微透镜形成在所述下基板上; 以及围绕图像传感器同时与图像传感器间隔开并与上基板接触的密封线。 晶片级封装可能有用于具有使用通孔的电连接结构，而不需要常规晶片级封装中的接合线，电极焊盘和电极引线，因为封装过程是通过将用于上部 具有多个通孔的基板设置在用于下基板的晶片中

    Camera module package
    2.
    发明申请
    Camera module package 审中-公开
    相机模块包

    公开(公告)号：US20080296577A1

    公开(公告)日：2008-12-04

    申请号：US12155268

    申请日：2008-05-30

    申请人： Jingli Yuan ,  Won Kyu Jeung ,  Dae Jun Kim ,  Chang Hyun Lim ,  Jae Cheon Doh

    发明人： Jingli Yuan ,  Won Kyu Jeung ,  Dae Jun Kim ,  Chang Hyun Lim ,  Jae Cheon Doh

    IPC分类号： H01L31/00 ,  H01L21/02

    CPC分类号： H01L27/14618 ,  H01L27/14687 ,  H01L31/0203 ,  H01L31/02325 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2924/10253 ,  H01L2924/3025 ,  H01L2924/00014 ,  H01L2924/00

    摘要： There is provided a camera module package including: a substrate having an image sensor disposed on one surface thereof and a pad electrically connected to the image sensor; a protective cap adhered onto the substrate by an adhesive surrounding the image sensor to seal the image sensor, the protective cap transmitting light; and a supporting part surrounding the protective cap, the supporting part adhering and supporting at least one lens formed corresponding to the image sensor. The camera module package is reduced in thickness and size, and minimized in an error of a focal length between the lens and the image sensor, thereby achieving accuracy and high reliability.

    摘要翻译： 提供了一种照相机模块包装，包括：具有设置在其一个表面上的图像传感器的基板和与图像传感器电连接的焊盘; 保护盖通过围绕图像传感器的粘合剂附着在基板上，以密封图像传感器，保护盖透射光; 以及围绕保护盖的支撑部分，支撑部分粘附并支撑形成对应于图像传感器的至少一个透镜。 相机模块包装的厚度和尺寸减小，并且在透镜和图像传感器之间的焦距误差最小化，从而实现精度和高可靠性。

    Wafer level package fabrication method
    3.
    发明授权
    Wafer level package fabrication method 有权
    晶圆级封装制造方法

    公开(公告)号：US07696004B2

    公开(公告)日：2010-04-13

    申请号：US12155317

    申请日：2008-06-02

    申请人： Jingli Yuan ,  Jae Cheon Doh ,  Si Joong Yang ,  In Goo Kang ,  Seung Wook Park

    发明人： Jingli Yuan ,  Jae Cheon Doh ,  Si Joong Yang ,  In Goo Kang ,  Seung Wook Park

    IPC分类号： H01L21/00

    CPC分类号： H01L23/10 ,  H01L21/76898 ,  H01L2924/0002 ,  H03H9/105 ,  H03H9/1092 ,  H01L2924/00

    摘要： Provided is a wafer level package fabrication method. The method includes providing a device substrate wafer including one or more devices on an upper surface thereof, and a bonding pad electrically connected to the device, providing a bonding seal surrounding the device along the bonding pad, bonding a cap substrate wafer to the device substrate wafer through the bonding seal, the cap substrate wafer having a via formed in a region corresponding to the bonding pad, forming an external terminal on the cap substrate wafer, the external terminal being electrically connected to the bonding pad, and cutting the cap substrate wafer and the device substrate wafer along a cutting line to individually separate a plurality of wafer level packages. The method is conducive to reducing product size for miniaturization, is capable of performing a bonding process without wafer deformation or damage, and increases freedom in wafer material selection.

    摘要翻译： 提供了晶片级封装制造方法。 该方法包括提供在其上表面上包括一个或多个器件的器件衬底晶片和电连接到该器件的焊盘，提供围绕该焊盘的器件的接合密封，将盖衬底晶片接合到器件衬底 晶片通过接合密封，所述盖基板晶片具有形成在与所述接合焊盘相对应的区域中的通孔，在所述盖基板晶片上形成外部端子，所述外部端子电连接到所述接合焊盘，以及切割所述盖基板晶片 以及沿着切割线的装置基板晶片，以单独分离多个晶片级封装。 该方法有利于减小产品尺寸以实现小型化，能够进行没有晶片变形或损坏的接合工艺，并增加晶片材料选择的自由度。

    Wafer level package fabrication method
    4.
    发明申请
    Wafer level package fabrication method 有权
    晶圆级封装制造方法

    公开(公告)号：US20080299706A1

    公开(公告)日：2008-12-04

    申请号：US12155317

    申请日：2008-06-02

    申请人： Jingli Yuan ,  Jae Cheon Doh ,  Si Joong Yang ,  In Goo Kang ,  Seung Wook Park

    发明人： Jingli Yuan ,  Jae Cheon Doh ,  Si Joong Yang ,  In Goo Kang ,  Seung Wook Park

    IPC分类号： H01L21/50

    CPC分类号： H01L23/10 ,  H01L21/76898 ,  H01L2924/0002 ,  H03H9/105 ,  H03H9/1092 ,  H01L2924/00

    摘要： Provided is a wafer level package fabrication method. The method includes providing a device substrate wafer including one or more devices on an upper surface thereof, and a bonding pad electrically connected to the device, providing a bonding seal surrounding the device along the bonding pad, bonding a cap substrate wafer to the device substrate wafer through the bonding seal, the cap substrate wafer having a via formed in a region corresponding to the bonding pad, forming an external terminal on the cap substrate wafer, the external terminal being electrically connected to the bonding pad, and cutting the cap substrate wafer and the device substrate wafer along a cutting line to individually separate a plurality of wafer level packages. The method is conducive to reducing product size for miniaturization, is capable of performing a bonding process without wafer deformation or damage, and increases freedom in wafer material selection.

    摘要翻译： 提供了晶片级封装制造方法。 该方法包括提供在其上表面上包括一个或多个器件的器件衬底晶片和电连接到该器件的焊盘，提供围绕该焊盘的器件的接合密封，将盖衬底晶片接合到器件衬底 晶片通过接合密封，所述盖基板晶片具有形成在与所述接合焊盘相对应的区域中的通孔，在所述盖基板晶片上形成外部端子，所述外部端子电连接到所述接合焊盘，以及切割所述盖基板晶片 以及沿着切割线的装置基板晶片，以单独分离多个晶片级封装。 该方法有利于减小产品尺寸以实现小型化，能够进行没有晶片变形或损坏的接合工艺，并增加晶片材料选择的自由度。

    Apparatus and method for inspecting defects of a circuit pattern formed on a substrate using a laser and a non-contact capacitor sensor
    5.
    发明授权
    Apparatus and method for inspecting defects of a circuit pattern formed on a substrate using a laser and a non-contact capacitor sensor 失效
    使用激光和非接触式电容传感器来检查形成在基板上的电路图案的缺陷的装置和方法

    公开(公告)号：US08410465B2

    公开(公告)日：2013-04-02

    申请号：US12716948

    申请日：2010-03-03

    申请人： Seung Seoup Lee ,  Jae Cheon Doh ,  In Kyung Park

    发明人： Seung Seoup Lee ,  Jae Cheon Doh ,  In Kyung Park

    IPC分类号： G01N21/86

    CPC分类号： G01R31/309

    摘要： An apparatus for inspecting defects in a circuit pattern is described. The apparatus includes at least one laser unit for radiating a laser beam onto a first end of a circuit pattern formed on a substrate. The apparatus also includes a capacitor sensor disposed opposite a second end of the circuit pattern, which is connected to the first end of the circuit pattern through a via hole, in a non-contact manner. The apparatus also includes a voltage source connected to the capacitor sensor and configured to apply a voltage. The apparatus also includes a measurement unit connected to the capacitor sensor and configured to detect variation in impedance generated in the capacitor sensor.

    摘要翻译： 描述了用于检查电路图案中的缺陷的装置。 该装置包括用于将激光束照射到形成在基板上的电路图案的第一端上的至少一个激光单元。 该装置还包括电容传感器，该电容器传感器与电路图案的第二端相对设置，其以非接触方式通过通孔连接到电路图案的第一端。 该装置还包括连接到电容器传感器并被配置为施加电压的电压源。 该装置还包括连接到电容器传感器并被配置为检测在电容器传感器中产生的阻抗变化的测量单元。

    3D power module package
    6.
    发明授权
    3D power module package 有权
    3D电源模块封装

    公开(公告)号：US08842438B2

    公开(公告)日：2014-09-23

    申请号：US13177270

    申请日：2011-07-06

    申请人： Tae Hoon Kim ,  Jae Cheon Doh ,  Seog Moon Choi

    发明人： Tae Hoon Kim ,  Jae Cheon Doh ,  Seog Moon Choi

    IPC分类号： H05K7/00 ,  H01L23/34 ,  H01L23/31 ,  H01L23/495 ,  H01L23/433 ,  H01L25/16

    CPC分类号： H01L23/3121 ,  H01L23/4334 ,  H01L23/49531 ,  H01L23/49575 ,  H01L25/16 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Disclosed herein is a 3D power module package, including: a power converting unit packaged to include a heat radiating substrate, a power device connected to the heat radiating substrate, and a lead frame; a controlling unit packaged to include a controlling unit substrate and IC and controlling devices mounted on an upper portion of the controlling unit substrate; and an electrical connecting unit electrically connecting the packaged power converting unit and the packaged controlling unit.

    摘要翻译： 本文公开了一种3D功率模块封装，包括：封装成包括散热基板的功率转换单元，连接到散热基板的功率器件和引线框架; 控制单元，其被封装成包括控制单元基板和IC以及安装在所述控制单元基板的上部的控制装置; 以及电连接单元，电连接所述封装的电力转换单元和所述封装的控制单元。

    3D POWER MODULE PACKAGE
    8.
    发明申请
    3D POWER MODULE PACKAGE 有权
    3D电源模块封装

    公开(公告)号：US20120162931A1

    公开(公告)日：2012-06-28

    申请号：US13177270

    申请日：2011-07-06

    申请人： Tae Hoon Kim ,  Jae Cheon Doh ,  Seog Moon Choi

    发明人： Tae Hoon Kim ,  Jae Cheon Doh ,  Seog Moon Choi

    IPC分类号： H05K7/00

    CPC分类号： H01L23/3121 ,  H01L23/4334 ,  H01L23/49531 ,  H01L23/49575 ,  H01L25/16 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Disclosed herein is a 3D power module package, including: a power converting unit packaged to include a heat radiating substrate, a power device connected to the heat radiating substrate, and a lead frame; a controlling unit packaged to include a controlling unit substrate and IC and controlling devices mounted on an upper portion of the controlling unit substrate; and an electrical connecting unit electrically connecting the packaged power converting unit and the packaged controlling unit.

    摘要翻译： 本文公开了一种3D功率模块封装，包括：封装成包括散热基板的功率转换单元，连接到散热基板的功率器件和引线框架; 控制单元，其被封装成包括控制单元基板和IC以及安装在所述控制单元基板的上部的控制装置; 以及电连接单元，电连接所述封装的电力转换单元和所述封装的控制单元。

    APPARATUS AND METHOD FOR INSPECTING DEFECTS IN CIRCUIT PATTERN
    9.
    发明申请
    APPARATUS AND METHOD FOR INSPECTING DEFECTS IN CIRCUIT PATTERN 失效
    用于检查电路图中缺陷的装置和方法

    公开(公告)号：US20110128011A1

    公开(公告)日：2011-06-02

    申请号：US12716948

    申请日：2010-03-03

    申请人： Seung Seoup LEE ,  Jae Cheon Doh ,  In Kyung Park

    发明人： Seung Seoup LEE ,  Jae Cheon Doh ,  In Kyung Park

    IPC分类号： G01R31/26 ,  G01R31/02

    CPC分类号： G01R31/309

    摘要： Disclosed herein is an apparatus and method for inspecting defects in a circuit pattern. In the inspection apparatus and method, a laser beam is radiated by a laser unit onto a first end of a circuit pattern, and variation in impedance of a capacitor sensor disposed at a second end of the circuit pattern is measured, thus measuring the open/short circuits of the circuit pattern.Accordingly, the inspection apparatus and method are advantageous in that defects in the circuit pattern can be measured in a non-contact manner, so that the consumption of pin probes can be reduced, and the reliability of the measurement of defects in the circuit pattern can be improved.

    摘要翻译： 本文公开了一种用于检查电路图案中的缺陷的装置和方法。 在检查装置和方法中，通过激光单元将激光束照射到电路图案的第一端，并且测量设置在电路图案的第二端的电容器传感器的阻抗的变化，从而测量开路/ 电路图案短路。 因此，检查装置和方法的优点在于，可以以非接触的方式测量电路图案的缺陷，从而可以减少引脚探针的消耗，并且电路图案中的缺陷的测量的可靠性可以 要改进