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    VERTICAL MEMORY DEVICES AND METHODS OF MANUFACTURING THE SAME
    5.
    发明申请
    VERTICAL MEMORY DEVICES AND METHODS OF MANUFACTURING THE SAME 有权
    垂直存储器件及其制造方法

    公开(公告)号：US20120098048A1

    公开(公告)日：2012-04-26

    申请号：US13221380

    申请日：2011-08-30

    申请人： Byeong-In CHOE ,  Jae-Hoon JANG ,  Sun-Il SHIM ,  Han-Soo KIM ,  Jin-Man HAN

    发明人： Byeong-In CHOE ,  Jae-Hoon JANG ,  Sun-Il SHIM ,  Han-Soo KIM ,  Jin-Man HAN

    IPC分类号： H01L29/792 ,  H01L21/20

    CPC分类号： H01L27/11582 ,  H01L29/7926

    摘要： A vertical memory device includes a channel, a ground selection line (GSL), word lines and a string selection line (SSL). The channel extends in a first direction substantially perpendicular to a top surface of a substrate, and a thickness of the channel is different according to height. The GSL, the word lines and the SSL are sequentially formed on a sidewall of the channel in the first direction and spaced apart from each other.

    摘要翻译： 垂直存储器件包括通道，接地选择线（GSL），字线和字符串选择线（SSL）。 通道沿基本上垂直于基板的顶表面的第一方向延伸，并且通道的厚度根据高度而不同。 GSL，字线和SSL顺序地形成在通道的第一方向的侧壁上并且彼此间隔开。

    NON-VOLATILE MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME
    8.
    发明申请
    NON-VOLATILE MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME 审中-公开
    非易失性存储器件及其制造方法

    公开(公告)号：US20080272434A1

    公开(公告)日：2008-11-06

    申请号：US11876638

    申请日：2007-10-22

    申请人： Jun-Beom PARK ,  Ki-Nam KIM ,  Soon-Moon JUNG ,  Jae-Hoon JANG

    发明人： Jun-Beom PARK ,  Ki-Nam KIM ,  Soon-Moon JUNG ,  Jae-Hoon JANG

    IPC分类号： H01L27/115 ,  H01L21/8247

    CPC分类号： H01L27/115 ,  H01L27/0688 ,  H01L27/11521 ,  H01L27/11551

    摘要： A non-volatile memory device and a method of manufacturing the same are disclosed. In the non-volatile memory device, first gate structures and first impurity diffusion regions are formed on a substrate. A first insulating interlayer is formed on the substrate. A semiconductor layer including second gate structures and second impurity diffusion regions is formed on the first insulating interlayer. A second insulating interlayer is formed on the semiconductor layer. A contact plug connecting the first impurity diffusion regions to the second impurity diffusion regions is formed. A common source line connected to the contact plug is formed on the second insulating interlayer. The common source line connected to the first and second impurity diffusion regions is formed over a top semiconductor layer.

    摘要翻译： 公开了一种非易失性存储器件及其制造方法。 在非易失性存储器件中，在衬底上形成第一栅极结构和第一杂质扩散区。 在基板上形成第一绝缘中间层。 在第一绝缘中间层上形成包括第二栅极结构和第二杂质扩散区的半导体层。 在半导体层上形成第二绝缘中间层。 形成将第一杂质扩散区域连接到第二杂质扩散区域的接触插塞。 在第二绝缘中间层上形成连接到接触塞的共同源极线。 连接到第一和第二杂质扩散区的公共源极线形成在顶部半导体层上。

    METHODS OF FABRICATING SEMICONDUCTOR INTEGRATED CIRCUITS USING SELECTIVE EPITAXIAL GROWTH AND PARTIAL PLANARIZATION TECHNIQUES AND SEMICONDUCTOR INTEGRATED CIRCUITS FABRICATED THEREBY
    10.
    发明申请
    METHODS OF FABRICATING SEMICONDUCTOR INTEGRATED CIRCUITS USING SELECTIVE EPITAXIAL GROWTH AND PARTIAL PLANARIZATION TECHNIQUES AND SEMICONDUCTOR INTEGRATED CIRCUITS FABRICATED THEREBY 审中-公开
    使用选择性外延生长和部分平面化技术制造半导体集成电路的方法和半导体集成电路制造的方法

    公开(公告)号：US20070241335A1

    公开(公告)日：2007-10-18

    申请号：US11766655

    申请日：2007-06-21

    申请人： Kun-Ho KWAK ,  Jae-Hoon JANG ,  Soon-Moon JUNG ,  Won-Seok CHO ,  Hoon LIM ,  Sung-Jin KIM ,  Byung-Jun HWANG ,  Jong-Hyuk KIM

    发明人： Kun-Ho KWAK ,  Jae-Hoon JANG ,  Soon-Moon JUNG ,  Won-Seok CHO ,  Hoon LIM ,  Sung-Jin KIM ,  Byung-Jun HWANG ,  Jong-Hyuk KIM

    IPC分类号： H01L27/108

    CPC分类号： H01L27/1108 ,  H01L27/11

    摘要： Methods of fabricating a semiconductor integrated circuit having thin film transistors using an SEG technique are provided. The methods include forming an inter-layer insulating layer on a single-crystalline semiconductor substrate. A single-crystalline semiconductor plug extends through the inter-layer insulating layer, and a single-crystalline epitaxial semiconductor pattern is in contact with the single-crystalline semiconductor plug on the inter-layer insulating layer. The single-crystalline epitaxial semiconductor pattern is at least partially planarized to form a semiconductor body layer on the inter-layer insulating layer, and the semiconductor body layer is patterned to form a semiconductor body. As a result, the semiconductor body includes at least a portion of the single-crystalline epitaxial semiconductor pattern. Thus, the semiconductor body has an excellent single-crystalline structure. Semiconductor integrated circuits fabricated using the methods are also provided.

    摘要翻译： 提供了使用SEG技术制造具有薄膜晶体管的半导体集成电路的方法。 所述方法包括在单晶半导体衬底上形成层间绝缘层。 单晶半导体插件延伸穿过层间绝缘层，并且单晶外延半导体图案与层间绝缘层上的单晶半导体插头接触。 单晶外延半导体图案至少部分地平坦化以在层间绝缘层上形成半导体本体层，并且对半导体本体层进行图案化以形成半导体本体。 结果，半导体本体包括单晶外延半导体图案的至少一部分。 因此，半导体本体具有优异的单晶结构。 还提供了使用这些方法制造的半导体集成电路。