利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

40 条记录 (耗时 0.025 秒)

    Frequency responsive bus coding
    3.
    发明授权
    Frequency responsive bus coding 有权
    频率响应总线编码

    公开(公告)号：US08451913B2

    公开(公告)日：2013-05-28

    申请号：US12971213

    申请日：2010-12-17

    申请人： Kyung Suk Oh ,  John Wilson ,  Joong-Ho Kim ,  Jihong Ren

    发明人： Kyung Suk Oh ,  John Wilson ,  Joong-Ho Kim ,  Jihong Ren

    IPC分类号： H04B3/00 ,  H04L25/00

    CPC分类号： H04L25/49 ,  H04L25/4915

    摘要： A data system permits bus encoding based on frequency of the bus and the frequency of switching on the bus so as to avoid undesirable frequency conditions such as a resonant condition or interference with other electrical devices. Transmission frequencies along one or more busses are monitored and used to control the encoding process, for example, an encoding process based on data bus inversion (DBI). The use of both a measure of an absolute number of logic levels (“DBI_DC”) and a measure of a number of logic level transitions relative to a prior signal (“DBI_AC”) provides a measure of control that may be used to compensate for both main and predriver switching noise.

    摘要翻译： 数据系统允许基于总线的频率和总线上的切换频率的总线编码，以避免不期望的频率条件，例如谐振条件或与其他电气设备的干扰。 监视一个或多个总线的传输频率并用于控制编码过程，例如，基于数据总线反转（DBI）的编码处理。 使用绝对数量逻辑电平（“DBI_DC”）的度量和相对于先前信号（“DBI_AC”）的逻辑电平转换的数量的度量提供了可用于补偿 主要和预先切换的开关噪声。

    FREQUENCY RESPONSIVE BUS CODING
    4.
    发明申请
    FREQUENCY RESPONSIVE BUS CODING 有权
    频率响应总线编码

    公开(公告)号：US20110084737A1

    公开(公告)日：2011-04-14

    申请号：US12971213

    申请日：2010-12-17

    申请人： Kyung Suk Oh ,  John Wilson ,  Joong-Ho Kim ,  Jihong Ren

    发明人： Kyung Suk Oh ,  John Wilson ,  Joong-Ho Kim ,  Jihong Ren

    IPC分类号： H03K3/00

    CPC分类号： H04L25/49 ,  H04L25/4915

    摘要： A data system permits bus encoding based on frequency of the bus and the frequency of switching on the bus so as to avoid undesirable frequency conditions such as a resonant condition or interference with other electrical devices. Transmission frequencies along one or more busses are monitored and used to control the encoding process, for example, an encoding process based on data bus inversion (DBI). The use of both a measure of an absolute number of logic levels (“DBI_DC”) and a measure of a number of logic level transitions relative to a prior signal (“DBI_AC”) provides a measure of control that may be used to compensate for both main and predriver switching noise.

    摘要翻译： 数据系统允许基于总线的频率和总线上的切换频率的总线编码，以避免不期望的频率条件，例如谐振条件或与其他电气设备的干扰。 监视一个或多个总线的传输频率并用于控制编码过程，例如，基于数据总线反转（DBI）的编码处理。 使用绝对数量逻辑电平（“DBI_DC”）的度量和相对于先前信号（“DBI_AC”）的逻辑电平转换的数量的度量提供了可用于补偿 主要和预先切换的开关噪声。

    Asymmetric communication on shared links
    6.
    发明授权
    Asymmetric communication on shared links 有权
    共享链路上的不对称通信

    公开(公告)号：US08588280B2

    公开(公告)日：2013-11-19

    申请号：US12809000

    申请日：2008-12-19

    申请人： Kyung Suk Oh ,  John Wilson ,  Frederick A. Ware ,  WooPoung Kim ,  Jade M. Kizer ,  Brian S. Leibowitz ,  Lei Luo ,  John Cronan Eble

    发明人： Kyung Suk Oh ,  John Wilson ,  Frederick A. Ware ,  WooPoung Kim ,  Jade M. Kizer ,  Brian S. Leibowitz ,  Lei Luo ,  John Cronan Eble

    IPC分类号： H04B1/38 ,  H04L5/16

    CPC分类号： G06F13/4243 ,  H04L25/4906 ,  Y02D10/14 ,  Y02D10/151

    摘要： Embodiments of a system that communicates bidirectional data between two devices via shared links is described. In this system, data is transmitted on the shared links by one of the devices using single-ended drivers, and corresponding symbols are received on the shared links by the other device using differential comparison circuits. The data may be encoded as a series of parallel codewords prior to transmission. Each shared link may communicate a respective symbol in each codeword, which can have one of two possible logical values (e.g., a logic 0 or a logic 1). The corresponding symbols received by the other device may comprise a parallel symbol set, and each of the differential comparison circuits may compare symbols received on pairs of the shared links. A decoder in the other device may decode a respective parallel symbol set from the outputs of the differential comparison circuits to recover the encoded data.

    摘要翻译： 描述通过共享链路在两个设备之间传送双向数据的系统的实施例。 在该系统中，使用单端驱动器的设备之一在共享链路上发送数据，并且使用差分比较电路由另一设备在共享链路上接收对应的符号。 数据可以在传输之前被编码为一系列并行码字。 每个共享链路可以在可以具有两个可能的逻辑值中的一个（例如，逻辑0或逻辑1）的每个码字中传送相应的符号。 由另一设备接收的对应符号可以包括并行符号集合，并且每个差分比较电路可以比较在共享链路对上接收到的符号。 另一设备中的解码器可以从差分比较电路的输出解码相应的并行符号集合，以恢复编码数据。

    ASYMMETRIC COMMUNICATION ON SHARED LINKS
    7.
    发明申请
    ASYMMETRIC COMMUNICATION ON SHARED LINKS 有权
    共享链路上的不对称通信

    公开(公告)号：US20100309964A1

    公开(公告)日：2010-12-09

    申请号：US12809000

    申请日：2008-12-19

    申请人： Kyung Suk Oh ,  John Wilson ,  Frederick Ware ,  WooPoung Kim ,  Jade M. Kizer ,  Brian S. Leibowitz ,  Lei Luo ,  John Cronan Eble

    发明人： Kyung Suk Oh ,  John Wilson ,  Frederick Ware ,  WooPoung Kim ,  Jade M. Kizer ,  Brian S. Leibowitz ,  Lei Luo ,  John Cronan Eble

    IPC分类号： H04B1/38

    CPC分类号： G06F13/4243 ,  H04L25/4906 ,  Y02D10/14 ,  Y02D10/151

    摘要： Embodiments of a system that communicates bidirectional data between two devices via shared links is described. In this system, data is transmitted on the shared links by one of the devices using single-ended drivers, and corresponding symbols are received on the shared links by the other device using differential comparison circuits. The data may be encoded as a series of parallel codewords prior to transmission. Each shared link may communicate a respective symbol in each codeword, which can have one of two possible logical values (e.g., a logic 0 or a logic 1). The corresponding symbols received by the other device may comprise a parallel symbol set, and each of the differential comparison circuits may compare symbols received on pairs of the shared links. A decoder in the other device may decode a respective parallel symbol set from the outputs of the differential comparison circuits to recover the encoded data.

    摘要翻译： 描述通过共享链路在两个设备之间传送双向数据的系统的实施例。 在该系统中，使用单端驱动器的设备之一在共享链路上发送数据，并且使用差分比较电路由另一设备在共享链路上接收对应的符号。 数据可以在传输之前被编码为一系列并行码字。 每个共享链路可以在可以具有两个可能的逻辑值中的一个（例如，逻辑0或逻辑1）的每个码字中传送相应的符号。 由另一设备接收的对应符号可以包括并行符号集合，并且每个差分比较电路可以比较在共享链路对上接收到的符号。 另一设备中的解码器可以从差分比较电路的输出解码相应的并行符号集合，以恢复编码数据。

    Signal lines with internal and external termination
    8.
    发明授权
    Signal lines with internal and external termination 有权
    具有内部和外部端接的信号线

    公开(公告)号：US08692573B2

    公开(公告)日：2014-04-08

    申请号：US13316046

    申请日：2011-12-09

    申请人： Kyung Suk Oh ,  Woopoung Kim ,  Huy M. Nguyen ,  Eugene C. Ho

    发明人： Kyung Suk Oh ,  Woopoung Kim ,  Huy M. Nguyen ,  Eugene C. Ho

    IPC分类号： H03K17/16 ,  H03K19/003

    CPC分类号： H03K19/0005 ,  G11C7/1048 ,  G11C7/1051 ,  G11C7/1057 ,  G11C7/1078 ,  G11C7/1084

    摘要： Embodiments of a memory controller are described. This memory controller communicates signals to a memory device via a signal line, which can be a data signal line or a command/address signal line. Termination of the signal line is divided between an external impedance outside of the memory controller and an internal impedance within the memory controller. The memory controller does not activate the external impedance prior to communicating the signals and, therefore, does not deactivate the external impedance after communicating the signals. The internal impedance of the memory controller can be enabled or disabled in order to reduce interface power consumption. Moreover, the internal impedance may be implemented using a passive component, an active component or both. For example, the internal impedance may include either or both an on-die termination and at least one driver.

    摘要翻译： 描述存储器控制器的实施例。 该存储器控制器通过信号线将信号传送到存储器件，信号线可以是数据信号线或命令/地址信号线。 信号线的终止在存储器控制器外部的外部阻抗和存储器控制器内的内部阻抗之间分配。 存储器控制器在通信信号之前不会激活外部阻抗，因此在通信信号之后不会禁用外部阻抗。 可以启用或禁用内存控制器的内部阻抗，以减少接口功耗。 此外，可以使用无源部件，有源部件或两者来实现内部阻抗。 例如，内部阻抗可以包括片上端接和至少一个驱动器中的一个或两者。

    INTEGRATED CIRCUIT DEVICE TIMING CALIBRATION
    9.
    发明申请
    INTEGRATED CIRCUIT DEVICE TIMING CALIBRATION 审中-公开
    集成电路设备时序校准

    公开(公告)号：US20130076425A1

    公开(公告)日：2013-03-28

    申请号：US13702261

    申请日：2011-03-21

    申请人： Kyung Suk Oh ,  Yohan U. Frans ,  Akash Bansal ,  Brian S. Leibowitz

    发明人： Kyung Suk Oh ,  Yohan U. Frans ,  Akash Bansal ,  Brian S. Leibowitz

    IPC分类号： H03K5/135

    CPC分类号： H03K5/135 ,  G11C7/1051 ,  G11C7/1066 ,  G11C7/1078 ,  G11C7/1093 ,  G11C29/022 ,  G11C29/023 ,  G11C29/028 ,  G11C2207/2254 ,  H04L7/0008 ,  H04L7/02 ,  H04L7/033 ,  H04L7/10

    摘要： Techniques for performing timing calibration for an integrated circuit (IC) device are described. During operation, a first integrated circuit device transmits a first calibration pattern having differently delayed rising edge transitions with respect to a timing reference. The first integrated circuit device additionally transmits a second calibration pattern having differently delayed falling edge transitions with respect to the timing reference. Next, the first integrated circuit generates a timing offset for transmitting data from the first integrated circuit device. This timing offset is derived from information received from a second integrated circuit device sampling the first calibration pattern and the second calibration pattern.

    摘要翻译： 描述了用于执行集成电路（IC）装置的定时校准的技术。 在操作期间，第一集成电路器件相对于定时参考传输具有不同延迟的上升沿转变的第一校准模式。 第一集成电路装置另外发送具有相对于定时参考具有不同延迟的下降沿跃迁的第二校准模式。 接下来，第一集成电路产生用于从第一集成电路器件发送数据的定时偏移。 该定时偏移是从对第一校准图案和第二校准图案采样的第二集成电路装置接收的信息导出的。

    Signal lines with internal and external termination
    10.
    发明授权
    Signal lines with internal and external termination 有权
    具有内部和外部端接的信号线

    公开(公告)号：US08130010B2

    公开(公告)日：2012-03-06

    申请号：US13022539

    申请日：2011-02-07

    申请人： Kyung Suk Oh ,  Woopoung Kim ,  Huy M. Nguyen ,  Eugene C. Ho

    发明人： Kyung Suk Oh ,  Woopoung Kim ,  Huy M. Nguyen ,  Eugene C. Ho

    IPC分类号： H03K17/16 ,  H03K19/003

    CPC分类号： H03K19/0005 ,  G11C7/1048 ,  G11C7/1051 ,  G11C7/1057 ,  G11C7/1078 ,  G11C7/1084

    摘要： Embodiments of a memory controller are described. This memory controller communicates signals to a memory device via a signal line, which can be a data signal line or a command/address signal line. Termination of the signal line is divided between an external impedance outside of the memory controller and an internal impedance within the memory controller. The memory controller does not activate the external impedance prior to communicating the signals and, therefore, does not deactivate the external impedance after communicating the signals. The internal impedance of the memory controller can be enabled or disabled in order to reduce interface power consumption. Moreover, the internal impedance may be implemented using a passive component, an active component or both. For example, the internal impedance may include either or both an on-die termination and at least one driver.

    摘要翻译： 描述存储器控制器的实施例。 该存储器控制器通过信号线将信号传送到存储器件，信号线可以是数据信号线或命令/地址信号线。 信号线的终止在存储器控制器外部的外部阻抗和存储器控制器内的内部阻抗之间分配。 存储器控制器在通信信号之前不会激活外部阻抗，因此在通信信号之后不会禁用外部阻抗。 可以启用或禁用内存控制器的内部阻抗，以减少接口功耗。 此外，内部阻抗可以使用无源部件，有源部件或两者来实现。 例如，内部阻抗可以包括片上端接和至少一个驱动器中的一个或两者。