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    System and method of generating hierarchical block-level timing constraints from chip-level timing constraints
    3.
    发明授权
    System and method of generating hierarchical block-level timing constraints from chip-level timing constraints 有权
    从芯片级定时约束产生分级块级时序约束的系统和方法

    公开(公告)号：US07926011B1

    公开(公告)日：2011-04-12

    申请号：US11621915

    申请日：2007-01-10

    申请人： Oleg Levitsky ,  Chien-Chu Kuo ,  Dinesh Gupta

    发明人： Oleg Levitsky ,  Chien-Chu Kuo ,  Dinesh Gupta

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5031 ,  G06F17/505 ,  G06F2217/84

    摘要： A system and method of designing an integrated circuit capable of deriving timing constraints for individual block-level circuits of an integrated circuit that are derived from the chip-level timing constraints and analysis. The block-level timing constraints are in the form of one or more logical timing constraint points at the input and output ports of block-level circuits. Each logical timing constraint points specifies a clock source used to clock data through the port, a delay parameter specifying data propagation delay backward from an input port and forward from an output port, and any timing exception associated with the data path. Using the logical timing constraint point, the circuit design system performs independent timing analysis and optimization of each block-level circuit. The system then reassembles the block-level circuits into a modified chip-level circuit for which timing closure can be achieved.

    摘要翻译： 一种设计集成电路的系统和方法，该集成电路能够导出从芯片级定时约束和分析导出的集成电路的各个块级电路的时序约束。 块级定时约束是块级电路的输入和输出端口处的一个或多个逻辑时序约束点的形式。 每个逻辑时序约束点指定用于通过端口对数据进行时钟源的时钟源，从输入端口向后指定数据传播延迟并从输出端口转发的延迟参数以及与数据路径相关联的任何定时异常。 使用逻辑时序约束点，电路设计系统对每个块级电路进行独立的时序分析和优化。 然后，系统将块级电路重新组装成可以实现时序闭合的修改的芯片级电路。

    Methods and apparatus for deskewing VCAT/LCAS members
    4.
    发明授权
    Methods and apparatus for deskewing VCAT/LCAS members 有权
    用于偏移VCAT / LCAS成员的方法和设备

    公开(公告)号：US07672315B2

    公开(公告)日：2010-03-02

    申请号：US11210127

    申请日：2005-08-23

    申请人： Dinesh Gupta ,  Dev Shankar Mukherjee ,  Rakesh Kumar Malik

    发明人： Dinesh Gupta ,  Dev Shankar Mukherjee ,  Rakesh Kumar Malik

    IPC分类号： H04L12/56

    CPC分类号： H04J3/0623 ,  H04J3/1611 ,  H04J2203/0094

    摘要： Write logic and read logic are coupled to SDRAM and a frame status table. VCG members are written into SDRAM by the write logic and an entry (based on the MFI and SQ) in the frame status table is maintained by the write logic for each member. The read logic scans the frame status table to identify the earliest frame number for which data is available in SDRAM. Based on the frame status and the address pointer offset, the read logic maintains a state table entry for each VCG member and a state for each VCG. According to the preferred embodiment, the read logic is provided in two parts separated by a temporary buffer. The first part of the read logic performs the functions described above and writes chunk data into the temporary buffer. The second part of the read logic reads byte data from the temporary buffer according to a selectable leak rate.

    摘要翻译： 写入逻辑和读取逻辑耦合到SDRAM和帧状态表。 VCG成员通过写逻辑写入SDRAM，帧状态表中的条目（基于MFI和SQ）由每个成员的写入逻辑维护。 读逻辑扫描帧状态表以识别SDRAM中数据可用的最早帧号。 基于帧状态和地址指针偏移，读逻辑维护每个VCG成员的状态表条目和每个VCG的状态。 根据优选实施例，读逻辑被提供在由临时缓冲器分开的两个部分中。 读逻辑的第一部分执行上述功能，并将块数据写入临时缓冲区。 读取逻辑的第二部分根据可选择的泄漏率从临时缓冲器读取字节数据。

    Systems for single pass parallel hierarchical timing closure of integrated circuit designs
    5.
    发明授权
    Systems for single pass parallel hierarchical timing closure of integrated circuit designs 有权
    集成电路设计的单程并行分层定时闭合系统

    公开(公告)号：US08539402B1

    公开(公告)日：2013-09-17

    申请号：US13716129

    申请日：2012-12-15

    申请人： Vivek Bhardwaj ,  Oleg Levitsky ,  Dinesh Gupta

    发明人： Vivek Bhardwaj ,  Oleg Levitsky ,  Dinesh Gupta

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5045 ,  G06F17/5031 ,  G06F17/505 ,  G06F17/5068 ,  G06F2217/62 ,  G06F2217/84

    摘要： In one embodiment of the invention, a method includes partitioning an integrated circuit design into a hierarchy of a top level and a plurality of partitions, wherein the top level includes a top level netlist and each partition includes a partition netlist; receiving data path timing budgets and clock path timing budgets for each of the plurality of partitions of the integrated circuit design; and generating a timing budget model of each partition in response to the respective data path timing budgets and clock path timing budgets, wherein each timing budget model includes an intra-partition clock timing constraint for each respective partition for independent implementation of the top level.

    摘要翻译： 在本发明的一个实施例中，一种方法包括将集成电路设计划分成顶层和多个分区的层级，其中顶层包括顶级网表，每个分区包括分区网表; 接收所述集成电路设计的所述多个分区中的每一个的数据路径定时预算和时钟路径时序预算; 以及响应于相应的数据路径定时预算和时钟路径定时预算，生成每个分区的定时预算模型，其中每个定时预算模型包括用于每个相应分区的分区内时钟定时约束，用于独立实现顶层。

    Combined hardware and software implementation of link capacity adjustment scheme (LCAS) in SONET (synchronous optical network) virtual concatenation (VCAT)
    6.
    发明授权
    Combined hardware and software implementation of link capacity adjustment scheme (LCAS) in SONET (synchronous optical network) virtual concatenation (VCAT) 有权
    在SONET（同步光网络）虚级联（VCAT）中组合硬件和软件实现链路容量调整方案（LCAS）

    公开(公告)号：US07558287B2

    公开(公告)日：2009-07-07

    申请号：US11210135

    申请日：2005-08-23

    申请人： Rakesh Kumar Malik ,  Dev Shankar Mukherjee ,  Harsh Chilwal ,  Dinesh Gupta

    发明人： Rakesh Kumar Malik ,  Dev Shankar Mukherjee ,  Harsh Chilwal ,  Dinesh Gupta

    IPC分类号： H04L12/28 ,  H04J3/16

    CPC分类号： H04J3/1611

    摘要： Combined hardware and software processing is applied in an end node of the network which includes mapping/demapping and deskewing. Most of the LCAS procedure is implemented in software so that it can be modified easily. Some of the procedure is implemented in hardware to meet stringent timing requirements. In particular, the handshaking protocol is implemented in software and the procedure for actually changing of the link capacity in response to the handshaking is implemented in hardware. The hardware and software communicate via a shared memory which includes a receive packet FIFO, receive control and status registers, a transmit packet FIFO, transmit control and status registers, and a transmit time slot interchange table.

    摘要翻译： 组合的硬件和软件处理应用于网络的终端节点，包括映射/解映射和去歪斜。 大多数LCAS程序都是以软件实现的，因此可以轻松修改。 一些程序在硬件中实现以满足严格的时序要求。 特别地，握手协议在软件中实现，并且响应于握手实际改变链路容量的过程在硬件中实现。 硬件和软件通过包括接收分组FIFO，接收控制和状态寄存器，发送分组FIFO，发送控制和状态寄存器以及发送时隙交换表的共享存储器进行通信。

    Methods and apparatus for deskewing VCAT/LCAS members
    7.
    发明申请
    Methods and apparatus for deskewing VCAT/LCAS members 有权
    用于偏移VCAT / LCAS成员的方法和设备

    公开(公告)号：US20070047593A1

    公开(公告)日：2007-03-01

    申请号：US11210127

    申请日：2005-08-23

    申请人： Dinesh Gupta ,  Dev Shankar Mukherjee ,  Rakesh Malik

    发明人： Dinesh Gupta ,  Dev Shankar Mukherjee ,  Rakesh Malik

    IPC分类号： H04J3/02

    CPC分类号： H04J3/0623 ,  H04J3/1611 ,  H04J2203/0094

    摘要： Write logic and read logic are coupled to SDRAM and a frame status table. VCG members are written into SDRAM by the write logic and an entry (based on the MFI and SQ) in the frame status table is maintained by the write logic for each member. The read logic scans the frame status table to identify the earliest frame number for which data is available in SDRAM. Based on the frame status and the address pointer offset, the read logic maintains a state table entry for each VCG member and a state for each VCG. According to the preferred embodiment, the read logic is provided in two parts separated by a temporary buffer. The first part of the read logic performs the functions described above and writes chunk data into the temporary buffer. The second part of the read logic reads byte data from the temporary buffer according to a selectable leak rate.

    摘要翻译： 写入逻辑和读取逻辑耦合到SDRAM和帧状态表。 VCG成员通过写逻辑写入SDRAM，帧状态表中的条目（基于MFI和SQ）由每个成员的写入逻辑维护。 读逻辑扫描帧状态表以识别SDRAM中数据可用的最早帧号。 基于帧状态和地址指针偏移，读逻辑维护每个VCG成员的状态表条目和每个VCG的状态。 根据优选实施例，读逻辑被提供在由临时缓冲器分开的两个部分中。 读逻辑的第一部分执行上述功能，并将块数据写入临时缓冲区。 读取逻辑的第二部分根据可选择的泄漏率从临时缓冲器读取字节数据。

    Methods for single pass parallel hierarchical timing closure of integrated circuit designs
    10.
    发明授权
    Methods for single pass parallel hierarchical timing closure of integrated circuit designs 有权
    集成电路设计的单程并行分层定时闭合方法

    公开(公告)号：US08935642B1

    公开(公告)日：2015-01-13

    申请号：US13716127

    申请日：2012-12-15

    申请人： Vivek Bhardwaj ,  Oleg Levitsky ,  Dinesh Gupta

    发明人： Vivek Bhardwaj ,  Oleg Levitsky ,  Dinesh Gupta

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5045 ,  G06F17/5031 ,  G06F17/505 ,  G06F17/5068 ,  G06F2217/62 ,  G06F2217/84

    摘要： In one embodiment of the invention, a method includes partitioning an integrated circuit design into a hierarchy of a top level and a plurality of partitions, wherein the top level includes a top level netlist and each partition includes a partition netlist; receiving data path timing budgets and clock path timing budgets for each of the plurality of partitions of the integrated circuit design; and generating a timing budget model of each partition in response to the respective data path timing budgets and clock path timing budgets, wherein each timing budget model includes an intra-partition clock timing constraint for each respective partition for independent implementation of the top level.

    摘要翻译： 在本发明的一个实施例中，一种方法包括将集成电路设计划分成顶层和多个分区的层级，其中顶层包括顶级网表，每个分区包括分区网表; 接收所述集成电路设计的所述多个分区中的每一个的数据路径定时预算和时钟路径时序预算; 以及响应于相应的数据路径定时预算和时钟路径定时预算，生成每个分区的定时预算模型，其中每个定时预算模型包括用于每个相应分区的分区内时钟定时约束，用于独立实现顶层。