摘要:
Disclosed is a method of making a multilayer ceramic product with thin layers, the method including the steps of: (a) providing a thick ceramic greensheet and a plurality of thin ceramic greensheets; (b) aligning and stacking the thin ceramic greensheet on the thick ceramic greensheet; (c) bonding the thin ceramic greensheet to the thick ceramic greensheet; (d) aligning and stacking one thin ceramic greensheet on the previous thin ceramic greensheet; (e) bonding the thin ceramic greensheet in step (d) to the previous thin ceramic greensheet; and (f) simultaneously forming at least one unfilled via in the stack of thick and thin ceramic greensheets.
摘要:
A system and method of designing an integrated circuit capable of deriving timing constraints for individual block-level circuits of an integrated circuit that are derived from the chip-level timing constraints and analysis. The block-level timing constraints are in the form of one or more logical timing constraint points at the input and output ports of block-level circuits. Each logical timing constraint points specifies a clock source used to clock data through the port, a delay parameter specifying data propagation delay backward from an input port and forward from an output port, and any timing exception associated with the data path. Using the logical timing constraint point, the circuit design system performs independent timing analysis and optimization of each block-level circuit. The system then reassembles the block-level circuits into a modified chip-level circuit for which timing closure can be achieved.
摘要:
Write logic and read logic are coupled to SDRAM and a frame status table. VCG members are written into SDRAM by the write logic and an entry (based on the MFI and SQ) in the frame status table is maintained by the write logic for each member. The read logic scans the frame status table to identify the earliest frame number for which data is available in SDRAM. Based on the frame status and the address pointer offset, the read logic maintains a state table entry for each VCG member and a state for each VCG. According to the preferred embodiment, the read logic is provided in two parts separated by a temporary buffer. The first part of the read logic performs the functions described above and writes chunk data into the temporary buffer. The second part of the read logic reads byte data from the temporary buffer according to a selectable leak rate.
摘要:
Process for producing multilayer ceramic substrates using greensheet technology and thin dielectric ceramic greensheets for miniaturization purposes. The process avoids the screening of the thin greensheets by forming self-supporting fusible particulate metal electrode layers, interposing them with the thin greensheets and sintering the assembly to form the multilayer substrates such as integrated capacitors.
摘要:
In one embodiment of the invention, a method includes partitioning an integrated circuit design into a hierarchy of a top level and a plurality of partitions, wherein the top level includes a top level netlist and each partition includes a partition netlist; receiving data path timing budgets and clock path timing budgets for each of the plurality of partitions of the integrated circuit design; and generating a timing budget model of each partition in response to the respective data path timing budgets and clock path timing budgets, wherein each timing budget model includes an intra-partition clock timing constraint for each respective partition for independent implementation of the top level.
摘要:
Combined hardware and software processing is applied in an end node of the network which includes mapping/demapping and deskewing. Most of the LCAS procedure is implemented in software so that it can be modified easily. Some of the procedure is implemented in hardware to meet stringent timing requirements. In particular, the handshaking protocol is implemented in software and the procedure for actually changing of the link capacity in response to the handshaking is implemented in hardware. The hardware and software communicate via a shared memory which includes a receive packet FIFO, receive control and status registers, a transmit packet FIFO, transmit control and status registers, and a transmit time slot interchange table.
摘要:
Write logic and read logic are coupled to SDRAM and a frame status table. VCG members are written into SDRAM by the write logic and an entry (based on the MFI and SQ) in the frame status table is maintained by the write logic for each member. The read logic scans the frame status table to identify the earliest frame number for which data is available in SDRAM. Based on the frame status and the address pointer offset, the read logic maintains a state table entry for each VCG member and a state for each VCG. According to the preferred embodiment, the read logic is provided in two parts separated by a temporary buffer. The first part of the read logic performs the functions described above and writes chunk data into the temporary buffer. The second part of the read logic reads byte data from the temporary buffer according to a selectable leak rate.
摘要:
A method and structure for personalizing a multi-layer substrate structure includes supplying a generic layer having electrical features and altering the electrical features to produce a personalized layer of the multi-layer substrate.
摘要:
Process for producing circuitized greensheets including multi-layer ceramic sub-laminates and composites comprising thin ceramic greensheets carrying and thin, fine line patterned conductive metal layers. The invention comprises releasably-supporting the thin greensheets on a temporary carrier support having an ablatable release layer, preferably over a patterned conductive layer, and filling the vias with conductive metal paste, whereby the thin greensheets are supported against warpage and distortion. The supported greensheets are formed as single layers, pairs and stacks thereof, as desired, and thereafter separated from the temporary support for use.
摘要:
In one embodiment of the invention, a method includes partitioning an integrated circuit design into a hierarchy of a top level and a plurality of partitions, wherein the top level includes a top level netlist and each partition includes a partition netlist; receiving data path timing budgets and clock path timing budgets for each of the plurality of partitions of the integrated circuit design; and generating a timing budget model of each partition in response to the respective data path timing budgets and clock path timing budgets, wherein each timing budget model includes an intra-partition clock timing constraint for each respective partition for independent implementation of the top level.