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    METHOD FOR MANUFACTURING THIN FILM TRANSISTOR ARRAY PANEL
    1.
    发明申请
    METHOD FOR MANUFACTURING THIN FILM TRANSISTOR ARRAY PANEL 有权
    制造薄膜晶体管阵列的方法

    公开(公告)号：US20120135555A1

    公开(公告)日：2012-05-31

    申请号：US13157806

    申请日：2011-06-10

    申请人： Jong-Hyun CHOUNG ,  Yang Ho BAE ,  Jean Ho SONG ,  O. Sung SEO ,  Sun-Young HONG ,  Hwa Yeul OH ,  Bong-Kyun KIM ,  Nam Seok SUH ,  Dong-Ju YANG ,  Wang Woo LEE

    发明人： Jong-Hyun CHOUNG ,  Yang Ho BAE ,  Jean Ho SONG ,  O. Sung SEO ,  Sun-Young HONG ,  Hwa Yeul OH ,  Bong-Kyun KIM ,  Nam Seok SUH ,  Dong-Ju YANG ,  Wang Woo LEE

    IPC分类号： H01L33/62

    CPC分类号： H01L21/32134 ,  G02F1/136227 ,  H01L27/1288 ,  H01L29/41733

    摘要： A method for manufacturing a thin film transistor array panel, including: sequentially forming a first silicon layer, a second silicon layer, a lower metal layer, and an upper metal layer on a gate insulating layer and a gate line; forming a first film pattern on the upper metal layer; forming a first lower metal pattern and a first upper metal pattern that includes a protrusion, by etching the upper metal layer and the lower metal layer; forming first and second silicon patterns by etching the first and second silicon layers; forming a second film pattern by ashing the first film pattern; forming a second upper metal pattern by etching the first upper metal pattern; forming a data line and a thin film transistor by etching the first lower metal pattern and the first and second silicon patterns; and forming a passivation layer and a pixel electrode on the resultant.

    摘要翻译： 一种制造薄膜晶体管阵列面板的方法，包括：在栅绝缘层和栅极线上依次形成第一硅层，第二硅层，下金属层和上金属层; 在上金属层上形成第一膜图案; 通过蚀刻上金属层和下金属层，形成第一下金属图案和包括突起的第一上金属图案; 通过蚀刻第一和第二硅层形成第一和第二硅图案; 通过灰化第一膜图案形成第二膜图案; 通过蚀刻第一上金属图案形成第二上金属图案; 通过蚀刻第一下金属图案和第一和第二硅图案来形成数据线和薄膜晶体管; 并在所得物上形成钝化层和像素电极。

    METHOD FOR MANUFACTURING THIN FILM TRANSISTOR ARRAY PANEL
    3.
    发明申请
    METHOD FOR MANUFACTURING THIN FILM TRANSISTOR ARRAY PANEL 有权
    制造薄膜晶体管阵列的方法

    公开(公告)号：US20120028421A1

    公开(公告)日：2012-02-02

    申请号：US13109686

    申请日：2011-05-17

    申请人： Dong-Ju YANG ,  Yu-Gwang JEONG ,  Jean-Ho SONG ,  Ki-Yeup LEE ,  Shin-Il CHOI ,  Tae-Woo KIM

    发明人： Dong-Ju YANG ,  Yu-Gwang JEONG ,  Jean-Ho SONG ,  Ki-Yeup LEE ,  Shin-Il CHOI ,  Tae-Woo KIM

    IPC分类号： H01L21/336

    CPC分类号： H01L27/1288 ,  H01L21/32138 ,  H01L27/1214 ,  H01L27/1255 ,  H01L29/458

    摘要： A method for manufacturing a thin film transistor array panel includes forming a gate line; forming an insulating layer on the gate line; forming first and second silicon layers first and second metal layers; forming a photoresist pattern having first and second portions; forming first and second metal patterns by etching the first and second metal layers; processing the first metal pattern with SF6 or SF6/He; forming silicon and semiconductor patterns by etching the second and first silicon layers; removing the first portion of the photoresist pattern; forming an upper layer of a data wire by wet etching the second metal pattern; forming a lower layer of the data wire and an ohmic contact by etching the first metal and amorphous silicon patterns; forming a passivation layer including a contact hole on the upper layer; and forming a pixel electrode on the passivation layer.

    摘要翻译： 薄膜晶体管阵列板的制造方法包括：形成栅极线; 在栅极线上形成绝缘层; 第一和第二硅层第一和第二金属层; 形成具有第一和第二部分的光致抗蚀剂图案; 通过蚀刻第一和第二金属层形成第一和第二金属图案; 用SF6或SF6 / He处理第一金属图案; 通过蚀刻第二和第一硅层形成硅和半导体图案; 去除光致抗蚀剂图案的第一部分; 通过湿法蚀刻第二金属图案形成数据线的上层; 通过蚀刻第一金属和非晶硅图案形成数据线的下层和欧姆接触; 在上层形成包括接触孔的钝化层; 以及在所述钝化层上形成像素电极。

    THIN FILM TRANSISTOR PANEL AND MANUFACTURING METHOD OF THE SAME
    5.
    发明申请
    THIN FILM TRANSISTOR PANEL AND MANUFACTURING METHOD OF THE SAME 审中-公开
    薄膜晶体管面板及其制造方法

    公开(公告)号：US20090224257A1

    公开(公告)日：2009-09-10

    申请号：US12390076

    申请日：2009-02-20

    申请人： Hong-Kee CHIN ,  Shin-Il CHOI ,  Sang-Gab KIM ,  Min-Seok OH ,  Yu-Gwang JEONG ,  Seung-Ha CHOI ,  Dong-Ju YANG

    发明人： Hong-Kee CHIN ,  Shin-Il CHOI ,  Sang-Gab KIM ,  Min-Seok OH ,  Yu-Gwang JEONG ,  Seung-Ha CHOI ,  Dong-Ju YANG

    IPC分类号： H01L33/00

    CPC分类号： H01L29/458 ,  H01L27/124

    摘要： A thin film transistor array panel includes a gate line formed on a substrate and including a gate electrode, a semiconductor layer formed on a surface of the substrate having the gate line, a data line formed on the semiconductor layer, insulatedly intersecting the gate line, and including a source electrode disposed on the gate electrode, a drain electrode separated from the source electrode by a channel, disposed on the gate electrode, and formed from the same layer as the data line, a passivation layer formed on the data line and the drain electrode and having a first contact hole exposing the drain electrode, and a pixel electrode formed on the passivation layer and contacting the drain electrode through the first contact hole. The data line and the drain electrode may include a first layer and a second layer formed on the first layer, a planar edge of the first layer protrudes from a planar edge of the second layer, and the first layer is formed by dry-etching and the second layer is formed by wet-etching.

    摘要翻译： 薄膜晶体管阵列面板包括形成在基板上并包括栅电极的栅极线，形成在具有栅极线的基板的表面上的半导体层，形成在半导体层上的与栅极线绝缘相交的数据线， 并且包括设置在栅电极上的源电极，通过沟道与源电极分离的漏极，设置在栅电极上，并由与数据线相同的层形成，形成在数据线上的钝化层和 漏极，并且具有暴露漏电极的第一接触孔，以及形成在钝化层上并通过第一接触孔接触漏电极的像素电极。 数据线和漏极可以包括形成在第一层上的第一层和第二层，第一层的平面边缘从第二层的平坦边缘突出，并且第一层通过干蚀刻形成， 第二层通过湿法蚀刻形成。

    THIN FILM TRANSISTOR ARRAY SUBSTRATE AND METHOD OF FABRICATING THE SAME
    6.
    发明申请
    THIN FILM TRANSISTOR ARRAY SUBSTRATE AND METHOD OF FABRICATING THE SAME 有权
    薄膜晶体管阵列基板及其制造方法

    公开(公告)号：US20100163862A1

    公开(公告)日：2010-07-01

    申请号：US12484116

    申请日：2009-06-12

    申请人： Dong-Ju YANG ,  Yu-Gwang Jeong ,  Ki-Yeup Lee ,  Sang-Gab Kim ,  Yun-Jong Yeo ,  Shin-Il Choi ,  Hong-Kee Chin ,  Seung-Ha Choi ,  Jung-Suk Bang

    发明人： Dong-Ju YANG ,  Yu-Gwang Jeong ,  Ki-Yeup Lee ,  Sang-Gab Kim ,  Yun-Jong Yeo ,  Shin-Il Choi ,  Hong-Kee Chin ,  Seung-Ha Choi ,  Jung-Suk Bang

    IPC分类号： H01L29/786 ,  H01L29/24 ,  H01L21/336

    CPC分类号： H01L27/1248 ,  H01L27/1214 ,  H01L27/1225 ,  H01L27/1288 ,  H01L29/7869

    摘要： A method of fabricating a thin film transistor array substrate is presented. The method entails forming a gate interconnection line on an insulating substrate, forming a gate insulating layer on the gate interconnection line, forming a semiconductor layer and a data interconnection line on the semiconductor layer, sequentially forming multiple passivation layers, etching the passivation layers down to a drain electrode that is an extension of the data interconnection line. The portion of the drain electrode that is exposed at this stage is a part of the drain electrode-pixel electrode contact portion. A pixel electrode is formed connected to the drain electrode. Two of the passivation layers have the same composition but are processed at different temperatures. A thin film transistor prepared in the above manner is also presented.

    摘要翻译： 提出了制造薄膜晶体管阵列基板的方法。 该方法需要在绝缘基板上形成栅极互连线，在栅极互连线上形成栅极绝缘层，在半导体层上形成半导体层和数据互连线，依次形成多个钝化层，将钝化层蚀刻到 作为数据互连线的延伸线的漏电极。 在该阶段暴露的漏电极的部分是漏极电极 - 像素电极接触部分的一部分。 形成连接到漏电极的像素电极。 两个钝化层具有相同的组成，但是在不同的温度下进行处理。 还提出了以上述方式制备的薄膜晶体管。

    METHOD OF FABRICATING A THIN FILM TRANSISTOR ARRAY SUBSTRATE
    7.
    发明申请
    METHOD OF FABRICATING A THIN FILM TRANSISTOR ARRAY SUBSTRATE 有权
    薄膜晶体管阵列基板的制作方法

    公开(公告)号：US20110297931A1

    公开(公告)日：2011-12-08

    申请号：US13210282

    申请日：2011-08-15

    申请人： Dong-Ju YANG ,  Yu-Gwang JEONG ,  Ki-Yeup LEE ,  Sang-Gab KIM ,  Yun-Jong YEO ,  Shin-Il CHOI ,  Hong-Kee CHIN ,  Seung-Ha CHOI ,  Jung-Suk BANG

    发明人： Dong-Ju YANG ,  Yu-Gwang JEONG ,  Ki-Yeup LEE ,  Sang-Gab KIM ,  Yun-Jong YEO ,  Shin-Il CHOI ,  Hong-Kee CHIN ,  Seung-Ha CHOI ,  Jung-Suk BANG

    IPC分类号： H01L29/786

    CPC分类号： H01L27/1248 ,  H01L27/1214 ,  H01L27/1225 ,  H01L27/1288 ,  H01L29/7869

    摘要： A method of fabricating a thin film transistor array substrate is presented. The method entails forming a gate interconnection line on an insulating substrate, forming a gate insulating layer on the gate interconnection line, forming a semiconductor layer and a data interconnection line on the semiconductor layer, sequentially forming multiple passivation layers, etching the passivation layers down to a drain electrode that is an extension of the data interconnection line. The portion of the drain electrode that is exposed at this stage is a part of the drain electrode-pixel electrode contact portion. A pixel electrode is formed connected to the drain electrode. Two of the passivation layers have the same composition but are processed at different temperatures. A thin film transistor prepared in the above manner is also presented.

    摘要翻译： 提出了制造薄膜晶体管阵列基板的方法。 该方法需要在绝缘基板上形成栅极互连线，在栅极互连线上形成栅极绝缘层，在半导体层上形成半导体层和数据互连线，依次形成多个钝化层，将钝化层蚀刻到 作为数据互连线的延伸线的漏电极。 在该阶段暴露的漏电极的部分是漏极电极 - 像素电极接触部分的一部分。 形成连接到漏电极的像素电极。 两个钝化层具有相同的组成，但是在不同的温度下进行处理。 还提出了以上述方式制备的薄膜晶体管。