公开(公告)号：US08871557B2

公开(公告)日：2014-10-28

申请号：US13601948

申请日：2012-08-31

Applicant: Joon Sung Lee ,  Yong Sun Yoon

Inventor： Joon Sung Lee ,  Yong Sun Yoon

IPC: H01L21/00 ,  H01L31/107

CPC classification number: H01L31/107 ,  H01L27/1446 ,  H01L27/14643 ,  H01L27/14689

Abstract: Provided are a photomultiplier and a manufacturing method thereof. The manufacturing method thereof may include forming a mask layer on an active region of a substrate doped with a first conductive type, ion implanting a second conductive type impurity opposite to the first conductive type into the substrate to form a first doped region in the active region under the mask layer and an non-active region exposed from the mask layer, forming a device isolation layer on the non-active region, removing the mask layer, and ion implanting the second conductive type impurity having a concentration higher than that of the first doped region into an upper portion of the first doped region in the active region to form a second doped region shallower than the first doped region.

Abstract translation: 提供一种光电倍增管及其制造方法。 其制造方法可以包括在掺杂有第一导电类型的衬底的有源区上形成掩模层，将与第一导电类型相反的第二导电类型杂质注入到衬底中以在有源区中形成第一掺杂区 在掩模层下面和从掩模层露出的非有源区，在非有源区上形成器件隔离层，去除掩模层，以及离子注入浓度高于第一导电型杂质的第二导电型杂质 掺杂区域进入有源区域中的第一掺杂区域的上部，以形成比第一掺杂区域浅的第二掺杂区域。

公开(公告)号：US08482092B2

公开(公告)日：2013-07-09

申请号：US13289256

申请日：2011-11-04

Applicant: Joon Sung Lee ,  Yong Sun Yoon

Inventor： Joon Sung Lee ,  Yong Sun Yoon

IPC: H01L31/07 ,  H01L29/00 ,  H01L21/00

CPC classification number: H01L31/103 ,  H01L27/1461 ,  H01L27/14683 ,  H01L31/107

Abstract: Provided are a silicon photomultiplier and method for fabricating silicon photomultiplier. The silicon photomultiplier includes a first conductive type semiconductor layer; a first conductive type buried layer disposed in a lower portion of the first conductive type semiconductor layer, and having a higher impurity concentration than the first conductive type semiconductor layer; quench resistors spaced from each other and disposed on the first conductive type semiconductor layer; a transparent insulator formed on the first conductive type semiconductor layer, and exposing the quench resistors; second conductive type doped layers disposed under the quench resistors to contact the first conductive type semiconductor layer; and a transparent electrode commonly connected to the quench resistors electrically.

Abstract translation: 提供了硅光电倍增管和制造硅光电倍增管的方法。 硅光电倍增管包括第一导电型半导体层; 第一导电型掩埋层，设置在第一导电类型半导体层的下部，并且具有比第一导电类型半导体层更高的杂质浓度; 淬火电阻彼此间隔开并设置在第一导电类型半导体层上; 形成在所述第一导电类型半导体层上的透明绝缘体，并暴露所述骤冷电阻器; 设置在所述骤冷电阻器下方的第二导电型掺杂层以接触所述第一导电类型半导体层; 以及通常连接到骤冷电阻器的透明电极。

公开(公告)号：US08860163B2

公开(公告)日：2014-10-14

申请号：US13324973

申请日：2011-12-13

Applicant: Joon Sung Lee ,  Yong Sun Yoon

Inventor： Joon Sung Lee ,  Yong Sun Yoon

IPC: H01L29/72 ,  G01T1/24 ,  G01J1/02 ,  H01L31/0232 ,  G01T1/20 ,  G01J1/04 ,  H01L27/146

CPC classification number: H01L31/02327 ,  G01J1/0214 ,  G01J1/0407 ,  G01T1/2002 ,  G01T1/248 ,  H01L27/14627

Abstract: Disclosed is an optical structure formed in an upper side of a semiconductor photomultiplier having a plurality of microcells. The optical structure includes: a first dielectric body formed in an upper side of a dead area between light receiving areas of the respective microcells and having a cross-sectional structure in which a lower side is wider than an upper side; and a second dielectric body formed in the upper side of the light receiving area of each microcell and having a cross-sectional structure in which a lower side is narrower than an upper side, and a refractive index of the second dielectric body is higher than that of the first dielectric body.

Abstract translation: 公开了一种形成在具有多个微小区的半导体光电倍增管的上侧的光学结构。 光学结构包括：第一电介质体，形成在各个微电池的光接收区域之间的死区的上侧，并且具有下侧宽于上侧的横截面结构; 以及形成在每个微电池的光接收区域的上侧的第二电介质体，并且具有下侧比上侧窄的截面结构，并且第二电介质的折射率高于 的第一绝缘体。

公开(公告)号：US20120153420A1

公开(公告)日：2012-06-21

申请号：US13324973

申请日：2011-12-13

Applicant: Joon Sung LEE ,  Yong Sun Yoon

Inventor： Joon Sung LEE ,  Yong Sun Yoon

IPC: H01L31/0232 ,  H01L31/18

CPC classification number: H01L31/02327 ,  G01J1/0214 ,  G01J1/0407 ,  G01T1/2002 ,  G01T1/248 ,  H01L27/14627

Abstract: Disclosed is an optical structure formed in an upper side of a semiconductor photomultiplier having a plurality of microcells. The optical structure includes: a first dielectric body formed in an upper side of a dead area between light receiving areas of the respective microcells and having a cross-sectional structure in which a lower side is wider than an upper side; and a second dielectric body formed in the upper side of the light receiving area of each microcell and having a cross-sectional structure in which a lower side is narrower than an upper side, and a refractive index of the second dielectric body is higher than that of the first dielectric body.

Abstract translation: 公开了一种形成在具有多个微小区的半导体光电倍增管的上侧的光学结构。 光学结构包括：第一电介质体，形成在各个微电池的光接收区域之间的死区的上侧，并且具有下侧宽于上侧的横截面结构; 以及形成在每个微电池的光接收区域的上侧的第二电介质体，并且具有下侧比上侧窄的截面结构，并且第二电介质的折射率高于 的第一绝缘体。

公开(公告)号：US07170044B2

公开(公告)日：2007-01-30

申请号：US10913398

申请日：2004-08-09

Applicant: Kun Sik Pakr ,  Seong Wook Yoo ,  Jong Moon Park ,  Yong Sun Yoon ,  Sang Gi Kim ,  Bo Woo Kim ,  Yoon Kyu Bae ,  Byung Won Lim ,  Jin Gun Koo

Inventor： Kun Sik Pakr ,  Seong Wook Yoo ,  Jong Moon Park ,  Yong Sun Yoon ,  Sang Gi Kim ,  Bo Woo Kim ,  Yoon Kyu Bae ,  Byung Won Lim ,  Jin Gun Koo

IPC: H01J40/14

CPC classification number: H01L31/02161 ,  H01L31/02019 ,  H01L31/022408

Abstract: Provided is a photodetector in which a transparent nonconductive material having an interface charge and a trapped charge is deposited on a semiconductor surface so as to form a depletion region on the surface of the semiconductor, and the depletion region is employed as an optical detecting region, thereby not only improving detection with respect to light having a wavelength of ultraviolet and blue ranges but also filtering light having a wavelength of visible and infrared ranges, and in which a fabricating process thereof is compatible with a universal silicon CMOS process.

Abstract translation: 提供了一种光电检测器，其中具有界面电荷和俘获电荷的透明非导电材料沉积在半导体表面上，以在半导体的表面上形成耗尽区，并且耗尽区被用作光学检测区域， 从而不仅能够提高对具有紫外线和蓝色范围的波长的光的检测，而且可以改善具有可见光和红外范围的波长的滤光，并且其制造方法与通用硅CMOS工艺相兼容。

公开(公告)号：US08402629B2

公开(公告)日：2013-03-26

申请号：US12635480

申请日：2009-12-10

Applicant: Dae Sik Lee ,  Yong Sun Yoon ,  Moon Youn Jung ,  Seon Hee Park

Inventor： Dae Sik Lee ,  Yong Sun Yoon ,  Moon Youn Jung ,  Seon Hee Park

IPC: B23P25/00 ,  B22D11/126 ,  A61M5/32 ,  B05D3/12

CPC classification number: A61M37/0015 ,  A61B5/14514 ,  A61B5/685 ,  A61M2037/0053 ,  Y10T29/49885 ,  Y10T29/4998 ,  Y10T156/1062

Abstract: Provided is a method of manufacturing a hollow microneedle structure. The method includes coating a hollow core having a predetermined section and being long in a lengthwise direction with a coating solution, and solidifying the coating solution to form a coating layer, depositing a metal seed layer on the coating layer, plating the seed metal layer with a metal to form a plated layer, cutting the hollow core having the plated layer at an inclination angle with respect to the lengthwise direction for form a surface inclination, and removing the hollow core and the coating layer to form a hollow microneedle structure. Thus, the hollow microneedle structure can be manufactured to have such diameter, length, hardness, and inclination angle as to minimize pain. By use of the hollow core, the microneedle structure can have vertical microneedles with a uniform inner diameter.

Abstract translation: 提供一种制造中空微针结构的方法。 该方法包括用涂布溶液涂布具有预定部分并在长度方向上长的中空芯，并固化涂布溶液以形成涂层，在涂层上沉积金属籽晶层，将种子金属层与 金属以形成镀层，切割具有相对于长度方向的倾斜角度的镀层的中空芯以形成表面倾斜，并且移除中空芯和涂层以形成中空微针结构。 因此，可以制造中空微针结构以具有使疼痛最小化的直径，长度，硬度和倾斜角度。 通过使用中空芯，微针结构可以具有均匀内径的垂直微针。

公开(公告)号：US20110005669A1

公开(公告)日：2011-01-13

申请号：US12635480

申请日：2009-12-10

Applicant: Dae Sik LEE ,  Yong Sun Yoon ,  Moon Youn Jung ,  Seon Hee Park

Inventor： Dae Sik LEE ,  Yong Sun Yoon ,  Moon Youn Jung ,  Seon Hee Park

IPC: B05D7/00 ,  B05D3/12 ,  B32B38/00

CPC classification number: A61M37/0015 ,  A61B5/14514 ,  A61B5/685 ,  A61M2037/0053 ,  Y10T29/49885 ,  Y10T29/4998 ,  Y10T156/1062

Abstract: Provided is a method of manufacturing a hollow microneedle structure. The method includes coating a hollow core having a predetermined section and being long in a lengthwise direction with a coating solution, and solidifying the coating solution to form a coating layer, depositing a metal seed layer on the coating layer, plating the seed metal layer with a metal to form a plated layer, cutting the hollow core having the plated layer at an inclination angle with respect to the lengthwise direction to form a surface inclination, and removing the hollow core and the coating layer to form a hollow. Thus, the hollow microneedle structure can be manufactured to have such diameter, length, hardness, and inclination angle as to minimize pain. By use of the hollow core, the microneedle structure can have vertical microneedles with a uniform inner diameter.

Abstract translation: 提供一种制造中空微针结构的方法。 该方法包括用涂布溶液涂布具有预定部分并在长度方向上长的中空芯，并固化涂布溶液以形成涂层，在涂层上沉积金属籽晶层，将种子金属层与 金属以形成镀层，切割具有相对于长度方向的倾斜角度的镀层的中空芯，以形成表面倾斜，并且移除中空芯和涂层以形成中空部。 因此，可以制造中空微针结构以具有使疼痛最小化的直径，长度，硬度和倾斜角度。 通过使用中空芯，微针结构可以具有均匀内径的垂直微针。

公开(公告)号：US07141464B2

公开(公告)日：2006-11-28

申请号：US11179983

申请日：2005-07-12

Applicant: Jong Moon Park ,  Kun Sik Park ,  Seong Wook Yoo ,  Yong Sun Yoon ,  Sang Gi Kim ,  Yoon Kyu Bae ,  Byung Won Lim ,  Jin Gun Koo ,  Bo Woo Kim

Inventor： Jong Moon Park ,  Kun Sik Park ,  Seong Wook Yoo ,  Yong Sun Yoon ,  Sang Gi Kim ,  Yoon Kyu Bae ,  Byung Won Lim ,  Jin Gun Koo ,  Bo Woo Kim

IPC: H01L21/338

CPC classification number: H01L21/28587

Abstract: Provided is a method of fabricating a T-type gate including the steps of: forming a first photoresist layer, a blocking layer and a second photoresist layer to a predetermined thickness on a substrate, respectively; forming a body pattern of a T-type gate on the second photoresist layer and the blocking layer; exposing a predetermined portion of the second photoresist layer to form a head pattern of the T-type gate, and performing a heat treatment process to generate cross linking at a predetermined region of the second photoresist layer except for the head pattern of the T-type gate; performing an exposure process on an entire surface of the resultant structure, and then removing the exposed portion; and forming a metal layer of a predetermined thickness on an entire surface of the resultant structure, and then removing the first photoresist layer, the blocking layer, the predetermined region of the second photoresist layer in which the cross linking are generated, and the metal layer, whereby it is possible to readily perform a compound semiconductor device manufacturing process, and to reduce manufacturing cost by means of the increase of manufacturing yield and the simplification of manufacturing processes.

Abstract translation: 提供一种制造T型栅极的方法，包括以下步骤：分别在衬底上形成预定厚度的第一光致抗蚀剂层，阻挡层和第二光致抗蚀剂层; 在所述第二光致抗蚀剂层和所述阻挡层上形成T型栅极的主体图案; 暴露第二光致抗蚀剂层的预定部分以形成T型栅极的头部图案，并且进行热处理工艺以在除了T型的头部图案之外的第二光致抗蚀剂层的预定区域处产生交联 门; 在所得结构的整个表面上进行曝光处理，然后去除所述暴露部分; 在所得结构的整个表面上形成预定厚度的金属层，然后去除第一光致抗蚀剂层，阻挡层，产生交联的第二光致抗蚀剂层的预定区域和金属层 ，由此可以容易地进行化合物半导体器件制造工艺，并且通过增加制造成品率和简化制造工艺来降低制造成本。

公开(公告)号：US20090146238A1

公开(公告)日：2009-06-11

申请号：US12195166

申请日：2008-08-20

Applicant: Yong Sun Yoon ,  Kun Sik Park ,  Jong Moon Park ,  Bo Woo Kim ,  Jin Yeong Kang

Inventor： Yong Sun Yoon ,  Kun Sik Park ,  Jong Moon Park ,  Bo Woo Kim ,  Jin Yeong Kang

IPC: H01L31/103 ,  H01L31/18

CPC classification number: H01L31/107

Abstract: A complementary metal-oxide semiconductor (CMOS)-based planar type avalanche photo diode (APD) using a silicon epitaxial layer and a method of manufacturing the APD, the photo diode including: a substrate; a well layer of a first conductivity type formed in the substrate; an avalanche embedded junction formed in the well layer of the first conductivity type by low energy ion implantation; the silicon epitaxial layer formed in the avalanche embedded junction; a doping area of a second conductivity type opposite to the first conductive type, formed from a portion of a surface of the well layer of the first conductivity type in the avalanche embedded junction and forming a p-n junction; positive and negative electrodes formed on the doping area of the second conductivity type and the well layer of the first conductivity type separated from the doping area of the second conductivity type, respectively; and an oxide layer formed on an overall surface excluding a window where the positive and negative electrodes are formed.

Abstract translation: 使用硅外延层的基于互补金属氧化物半导体（CMOS）的平面型雪崩光电二极管（APD）和制造该APD的方法，所述光电二极管包括：衬底; 在衬底中形成的第一导电类型的阱层; 通过低能离子注入形成在第一导电类型的阱层中的雪崩嵌入结; 形成在雪崩嵌入结的硅外延层; 由所述第一导电类型的阱层的表面的一部分形成在所述雪崩嵌入结中并形成p-n结的与所述第一导电类型相反的第二导电类型的掺杂区域; 分别形成在第二导电类型的掺杂区域上的正极和负极以及从第二导电类型的掺杂区域分离的第一导电类型的阱层; 以及形成在除了形成正极和负极的窗口之外的整个表面上的氧化物层。

公开(公告)号：US07855366B2

公开(公告)日：2010-12-21

申请号：US12111830

申请日：2008-04-29

Applicant: Kun Sik Park ,  Yong Sun Yoon ,  Bo Woo Kim ,  Jin Yeong Kang ,  Jong Moon Park ,  Seong Wook Yoo

Inventor： Kun Sik Park ,  Yong Sun Yoon ,  Bo Woo Kim ,  Jin Yeong Kang ,  Jong Moon Park ,  Seong Wook Yoo

IPC: G01J5/20

CPC classification number: G01J5/20 ,  H01L21/762 ,  H01L27/1203

Abstract: A BJT (bipolar junction transistor)-based uncooled IR sensor and a manufacturing method thereof are provided. The BJT-based uncooled IR sensor includes: a substrate; at least one BJT which is formed to be floated apart from the substrate; and a heat absorption layer which is formed on an upper surface of the at least one BJT, wherein the BJT changes an output value according heat absorbed through the heat absorption layer. Accordingly, it is possible to provide a BJT-based uncooled IR sensor capable of being implemented through a CMOS compatible process and obtaining more excellent temperature change detection characteristics.

Abstract translation: 提供了一种基于BJT（双极结型晶体管）的非制冷IR传感器及其制造方法。 基于BJT的非制冷红外传感器包括：基板; 至少一个BJT，其形成为与衬底分开浮动; 以及形成在所述至少一个BJT的上表面上的吸热层，其中所述BJT根据通过所述吸热层吸收的热量来改变输出值。 因此，可以提供能够通过CMOS兼容工艺实现的BJT系非冷却IR传感器，并获得更优异的温度变化检测特性。