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    Method of making dense vertical FET's
    2.
    发明授权
    Method of making dense vertical FET's 失效
    制造密集垂直FET的方法

    公开(公告)号：US4407058A

    公开(公告)日：1983-10-04

    申请号：US266231

    申请日：1981-05-22

    申请人： Joseph J. Fatula, Jr. ,  Paul L. Garbarino ,  Joseph F. Shepard

    发明人： Joseph J. Fatula, Jr. ,  Paul L. Garbarino ,  Joseph F. Shepard

    IPC分类号： H01L27/10 ,  H01L21/306 ,  H01L21/336 ,  H01L21/762 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/04 ,  H01L27/108 ,  H01L29/78 ,  H01L21/225

    CPC分类号： H01L29/66666 ,  H01L21/30608 ,  H01L21/762 ,  H01L29/7827

    摘要： A dielectrically isolated region of a monocrystalline substrate, which has a orientation, has a drain region of a field effect transistor (FET) in a surface having a (100) crystal orientation with the drain region being of opposite conductivity to the conductivity of the substrate. A gate channel extends into the substrate from the drain region and is surrounded at its upper end by the drain region. An enlarged recess extends into the substrate beneath the gate channel and has its walls of opposite conductivity to the conductivity of the substrate to form a source region and a plate of a capacitor when the FET is part of a storage cell. The source region has its upper end surrounded by the gate channel.

    摘要翻译： 具有<100>取向的单晶衬底的介电隔离区域在具有（100）晶体取向的表面中具有场效应晶体管（FET）的漏极区域，其漏极区域与导电性相反的导电性 的基底。 栅极沟道从漏极区域延伸到衬底中并且在其上端被漏极区域包围。 扩大的凹槽在栅极通道下延伸到衬底中，并且当FET是存储单元的一部分时，具有与衬底的导电性相反导电性的壁形成源极区域和电容器板。 源极区域的上端被栅极通道包围。

    Testing method and structure for leakage current characterization in the manufacture of dynamic RAM cells
    3.
    发明授权
    Testing method and structure for leakage current characterization in the manufacture of dynamic RAM cells 失效
    在动态RAM单元的制造中漏电流表征的测试方法和结构

    公开(公告)号：US4542340A

    公开(公告)日：1985-09-17

    申请号：US454900

    申请日：1982-12-30

    申请人： Satya N. Chakravarti ,  Paul L. Garbarino ,  Donald A. Miller

    发明人： Satya N. Chakravarti ,  Paul L. Garbarino ,  Donald A. Miller

    IPC分类号： H01L27/10 ,  H01L21/66 ,  H01L21/822 ,  H01L27/04 ,  H01L27/108 ,  G01R31/26 ,  G01R31/00

    CPC分类号： H01L27/108

    摘要： A testing method and structure for leakage current characterization in the manufacture of dynamic RAM cells; the testing structure includes two large gate-controlled diodes, each diode having a diffused junction which is substantially identical with that of the other diode, the gates of the diodes having different perimeter-to-area ratios, such that when testing is carried out, the leakage current components due to the contribution of the thin oxide area can be isolated from the perimeter-contributed components of the isolating thick oxide; dynamic testing can also be performed and, because of the small area for the test site, an "on chip" amplifier can be provided at the site.

    摘要翻译： 用于制造动态RAM单元的漏电流表征的测试方法和结构; 测试结构包括两个大的栅极控制二极管，每个二极管具有与另一个二极管基本相同的扩散结，二极管的栅极具有不同的周长与面积比，使得当进行测试时， 由于薄氧化物区域的贡献导致的漏电流成分可以从隔离厚氧化物的周边贡献成分中分离出来; 也可以进行动态测试，由于测试点的面积小，可以在现场提供“片上”放大器。

    Method for making an electrical contact to a silicon substrate through a relatively thin layer of silicon dioxide on the surface of the substrate
    6.
    发明授权
    Method for making an electrical contact to a silicon substrate through a relatively thin layer of silicon dioxide on the surface of the substrate 失效
    用于通过衬底表面上较薄的二氧化硅层与硅衬底电接触的方法

    公开(公告)号：US4341009A

    公开(公告)日：1982-07-27

    申请号：US213526

    申请日：1980-12-05

    申请人： Robert F. Bartholomew ,  Paul L. Garbarino ,  James R. Gardiner ,  Martin Revitz ,  Joseph F. Shepard

    发明人： Robert F. Bartholomew ,  Paul L. Garbarino ,  James R. Gardiner ,  Martin Revitz ,  Joseph F. Shepard

    IPC分类号： H01L21/28 ,  H01L21/285 ,  H01L29/78

    CPC分类号： H01L29/78 ,  H01L21/28525

    摘要： A buried electrical contact is made to a substrate of monocrystalline silicon through a relatively thin layer of silicon dioxide without causing damage to the relatively thin layer of silicon dioxide. This is accomplished through depositing a thin layer of polycrystalline silicon over the relatively thin layer of silicon dioxide prior to forming the opening in the relatively thin layer of silicon dioxide for the electrical contact to the substrate. After the thin layer of polycrystalline silicon is deposited, an opening is formed therein so that the thin layer of polycrystalline silicon functions as a mask to etch a corresponding opening in the relatively thin layer of silicon dioxide. Then, a layer of polycrystalline silicon is deposited over the exposed surface of the substrate and the thin layer of polycrystalline silicon to form the electrical contact through the opening in the relatively thin layer of silicon dioxide to the substrate.

    摘要翻译： 通过相对薄的二氧化硅层对单晶硅的衬底进行掩埋的电接触，而不会对相对薄的二氧化硅层造成损害。 这是通过在相对较薄的二氧化硅层上沉积薄层的多晶硅来实现的，然后在相对较薄的二氧化硅层中形成用于与基板的电接触的开口。 在沉积薄层多晶硅之后，在其中形成开口，使得多晶硅薄层用作掩模以蚀刻相对薄的二氧化硅层中的对应开口。 然后，在衬底的暴露表面和多晶硅薄层上沉积一层多晶硅，以形成通过相对薄的二氧化硅层中的开口到衬底的电接触。