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    Method for making an electrical contact to a silicon substrate through a relatively thin layer of silicon dioxide on the surface of the substrate
    5.
    发明授权
    Method for making an electrical contact to a silicon substrate through a relatively thin layer of silicon dioxide on the surface of the substrate 失效
    用于通过衬底表面上较薄的二氧化硅层与硅衬底电接触的方法

    公开(公告)号：US4341009A

    公开(公告)日：1982-07-27

    申请号：US213526

    申请日：1980-12-05

    申请人： Robert F. Bartholomew ,  Paul L. Garbarino ,  James R. Gardiner ,  Martin Revitz ,  Joseph F. Shepard

    发明人： Robert F. Bartholomew ,  Paul L. Garbarino ,  James R. Gardiner ,  Martin Revitz ,  Joseph F. Shepard

    IPC分类号： H01L21/28 ,  H01L21/285 ,  H01L29/78

    CPC分类号： H01L29/78 ,  H01L21/28525

    摘要： A buried electrical contact is made to a substrate of monocrystalline silicon through a relatively thin layer of silicon dioxide without causing damage to the relatively thin layer of silicon dioxide. This is accomplished through depositing a thin layer of polycrystalline silicon over the relatively thin layer of silicon dioxide prior to forming the opening in the relatively thin layer of silicon dioxide for the electrical contact to the substrate. After the thin layer of polycrystalline silicon is deposited, an opening is formed therein so that the thin layer of polycrystalline silicon functions as a mask to etch a corresponding opening in the relatively thin layer of silicon dioxide. Then, a layer of polycrystalline silicon is deposited over the exposed surface of the substrate and the thin layer of polycrystalline silicon to form the electrical contact through the opening in the relatively thin layer of silicon dioxide to the substrate.

    摘要翻译： 通过相对薄的二氧化硅层对单晶硅的衬底进行掩埋的电接触，而不会对相对薄的二氧化硅层造成损害。 这是通过在相对较薄的二氧化硅层上沉积薄层的多晶硅来实现的，然后在相对较薄的二氧化硅层中形成用于与基板的电接触的开口。 在沉积薄层多晶硅之后，在其中形成开口，使得多晶硅薄层用作掩模以蚀刻相对薄的二氧化硅层中的对应开口。 然后，在衬底的暴露表面和多晶硅薄层上沉积一层多晶硅，以形成通过相对薄的二氧化硅层中的开口到衬底的电接触。

    Method of making dense vertical FET's
    6.
    发明授权
    Method of making dense vertical FET's 失效
    制造密集垂直FET的方法

    公开(公告)号：US4407058A

    公开(公告)日：1983-10-04

    申请号：US266231

    申请日：1981-05-22

    申请人： Joseph J. Fatula, Jr. ,  Paul L. Garbarino ,  Joseph F. Shepard

    发明人： Joseph J. Fatula, Jr. ,  Paul L. Garbarino ,  Joseph F. Shepard

    IPC分类号： H01L27/10 ,  H01L21/306 ,  H01L21/336 ,  H01L21/762 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/04 ,  H01L27/108 ,  H01L29/78 ,  H01L21/225

    CPC分类号： H01L29/66666 ,  H01L21/30608 ,  H01L21/762 ,  H01L29/7827

    摘要： A dielectrically isolated region of a monocrystalline substrate, which has a orientation, has a drain region of a field effect transistor (FET) in a surface having a (100) crystal orientation with the drain region being of opposite conductivity to the conductivity of the substrate. A gate channel extends into the substrate from the drain region and is surrounded at its upper end by the drain region. An enlarged recess extends into the substrate beneath the gate channel and has its walls of opposite conductivity to the conductivity of the substrate to form a source region and a plate of a capacitor when the FET is part of a storage cell. The source region has its upper end surrounded by the gate channel.

    摘要翻译： 具有<100>取向的单晶衬底的介电隔离区域在具有（100）晶体取向的表面中具有场效应晶体管（FET）的漏极区域，其漏极区域与导电性相反的导电性 的基底。 栅极沟道从漏极区域延伸到衬底中并且在其上端被漏极区域包围。 扩大的凹槽在栅极通道下延伸到衬底中，并且当FET是存储单元的一部分时，具有与衬底的导电性相反导电性的壁形成源极区域和电容器板。 源极区域的上端被栅极通道包围。

    Vertical dual gate thin film transistor with self-aligned gates / offset drain
    8.
    发明授权
    Vertical dual gate thin film transistor with self-aligned gates / offset drain 失效
    具有自对准栅极/漏极漏极的垂直双栅极薄膜晶体管

    公开(公告)号：US5574294A

    公开(公告)日：1996-11-12

    申请号：US576103

    申请日：1995-12-22

    申请人： Joseph F. Shepard

    发明人： Joseph F. Shepard

    IPC分类号： H01L21/336 ,  H01L29/786 ,  H01L29/76 ,  H01L21/265

    CPC分类号： H01L29/6675 ,  H01L29/78618 ,  H01L29/78624 ,  H01L29/78642 ,  H01L29/78648

    摘要： A process for making a dual gated thin film transistor (TFT), having a sidewall channel and self-aligned gates and off-set drain is disclosed. A substrate having a top surface with insulating regions is provided. A bilayer having a polysilicon bottom layer and an insulating top layer, is patterned to form the bottom electrode of the TFT with an insulating layer over it. A first gate insulator is formed in contact with sides of the bottom electrode. A layer of second polysilicon having two end source and drain regions and a middle channel region is formed with the channel region being vertical along the side of the bottom electrode and overlying insulator layer and in contact with the first gate insulator. A second gate insulator is formed on the second polysilicon. A contact opening is etched in the insulating layers overlying the bottom electrode, in a region away from the second polysilicon to expose surface of part of the bottom electrode. A third polysilicon layer is deposited and patterned to have a horizontal region overlapping the contact opening to make contact to the bottom electrode, and to have sidewall electrode regions in contact with the second gate insulator and superadjacent to the channel region act as the top electrode of the TFT. The sidewall spacer electrode regions are connected to the horizontal regions of the third polysilicon. Thus the top and bottom electrode are also electrically connected together. The source and drain regions are doped selectively. By choice of implant conditions, the off-set region having a desired dopant concentration different from the device layer concentration, can be formed at the drain side of the dual gated TFT.

    摘要翻译： 公开了一种制造具有侧壁通道和自对准栅极和偏置漏极的双门控薄膜晶体管（TFT）的工艺。 提供了具有绝缘区域的顶面的基板。 将具有多晶硅底层和绝缘顶层的双层图案化以形成TFT上的绝缘层的TFT的底部电极。 第一栅极绝缘体形成为与底部电极的侧面接触。 形成具有两个端部源极和漏极区域以及中间沟道区域的第二多晶硅层，其中沟道区域沿着底部电极和上部绝缘体层的侧面是垂直的并且与第一栅极绝缘体接触。 在第二多晶硅上形成第二栅极绝缘体。 在覆盖底部电极的绝缘层中，在远离第二多晶硅的区域中蚀刻接触开口以暴露底部电极的一部分的表面。 第三多晶硅层被沉积和图案化以具有与接触开口重叠的水平区域以与底部电极接触，并且具有与第二栅极绝缘体接触并且与沟道区域相邻的侧壁电极区域用作顶部电极 TFT。 侧壁间隔电极区域连接到第三多晶硅的水平区域。 因此，顶部和底部电极也电连接在一起。 源区和漏区被选择性掺杂。 通过选择注入条件，可以在双门控TFT的漏极侧形成具有不同于器件层浓度的期望掺杂剂浓度的偏移区域。

    Method of forming integrated interconnect for very high density DRAMs
    9.
    发明授权
    Method of forming integrated interconnect for very high density DRAMs 失效
    形成非常高密度DRAM的集成互连的方法

    公开(公告)号：US5389559A

    公开(公告)日：1995-02-14

    申请号：US161763

    申请日：1993-12-02

    申请人： Chang-Ming Hsieh ,  Louis L. Hsu ,  Toshio Mii ,  Seiki Ogura ,  Joseph F. Shepard

    发明人： Chang-Ming Hsieh ,  Louis L. Hsu ,  Toshio Mii ,  Seiki Ogura ,  Joseph F. Shepard

    IPC分类号： H01L21/8242 ,  H01L27/108 ,  H01L21/70 ,  H01L27/00

    CPC分类号： H01L27/10861 ,  H01L27/10829

    摘要： A trench capacitor DRAM cell with Shallow Trench Isolation (STI), a self-aligned buried strap and the method of making the cell. A trench capacitor is defined in a substrate. The trench capacitor's polysilicon (poly) plate is recessed below the surface of the substrate and the trench sidewalls are exposed above the poly. A doped poly layer is deposited over the surface contacting both the sidewall and the trench capacitor's poly plate. Horizontal portions of the poly layer are removed either through chemmech polishing or Reactive Ion Etching (RIE). A shallow trench is formed, removing one formerly exposed trench sidewall and a portion of the trench capacitor's poly plate in order to isolate the DRAM cell from adjacent cells. The remaining poly strap, along the trench sidewall contacting the poly plate, is self aligned to contact the source of the DRAM Pass gate Field Effect Transistor (FET). After the shallow trench is filled with oxide, FET's are formed on the substrate, completing the cell. In an alternate embodiment, instead of recessing the poly plate, a shallow trench is formed spanning the entire width of the trench capacitor. The deposited polysilicon is selectively removed, having straps that strap the poly plate to the shallow trench sidewall.

    摘要翻译： 具有浅沟槽隔离（STI）的沟槽电容器DRAM单元，自对准掩埋带和制造电池的方法。 沟槽电容器限定在衬底中。 沟槽电容器的多晶硅（poly）板在衬底的表面下方凹入，并且沟槽侧壁暴露在聚合物上方。 在与侧壁和沟槽电容器的多晶硅板接触的表面上沉积掺杂的多晶硅层。 通过化学抛光或反应离子蚀刻（RIE）去除多层的水平部分。 形成浅沟槽，去除一个以前暴露的沟槽侧壁和沟槽电容器的多晶片的一部分，以便将DRAM单元与相邻单元隔离。 沿着与多晶硅板接触的沟槽侧壁的剩余多晶带自对准以接触DRAM通过栅极场效应晶体管（FET）的源极。 在浅沟槽充满氧化物之后，在衬底上形成FET，从而完成电池。 在替代实施例中，代替凹陷多晶硅，形成跨越沟槽电容器的整个宽度的浅沟槽。 选择性地去除沉积的多晶硅，具有将多晶板绑定到浅沟槽侧壁的带。

    DRAM cell having raised source, drain and isolation
    10.
    发明授权
    DRAM cell having raised source, drain and isolation 失效
    DRAM电池具有升高的源极，漏极和隔离

    公开(公告)号：US5369049A

    公开(公告)日：1994-11-29

    申请号：US169873

    申请日：1993-12-17

    申请人： Joyce E. Acocella ,  Louis L. Hsu ,  Seiki Ogura ,  Nivo Rovedo ,  Joseph F. Shepard

    发明人： Joyce E. Acocella ,  Louis L. Hsu ,  Seiki Ogura ,  Nivo Rovedo ,  Joseph F. Shepard

    IPC分类号： H01L27/108 ,  H01L27/00 ,  H01L21/70

    CPC分类号： H01L27/10829

    摘要： A method of forming a MOS DRAM cell having a trench capacitor in which the strap connection to the trench capacitor, the source, drain, and isolation are all raised above the surface of the single crystal silicon includes the steps of forming the trench capacitors, depositing a blanket gate stack including the gate oxide and a set of gate layers, and then depositing isolation members in apertures etched in the gate stack using the gate oxide as an etch stop. The same sidewalls that are used to form an LDD source and drain form a self-aligned aperture for a surface strap that insulates the strap from misaligned portions of the gate stack.

    摘要翻译： 一种形成具有沟槽电容器的MOS DRAM单元的方法，其中与沟槽电容器的带连接，源极，漏极和隔离都在单晶硅的表面上方升高，包括以下步骤：形成沟槽电容器， 包括栅极氧化物和一组栅极层的覆盖栅极堆叠，然后使用栅极氧化物作为蚀刻停止层，在隔离栅堆叠中蚀刻的孔中沉积隔离元件。 用于形成LDD源和漏极的相同侧壁形成用于将带与栅堆叠的未对准部分绝缘的表面带的自对准孔。