公开(公告)号：US4914502A

公开(公告)日：1990-04-03

申请号：US147038

申请日：1988-01-29

申请人： Joseph Lebowitz ,  William T. Lynch

发明人： Joseph Lebowitz ,  William T. Lynch

IPC分类号： H01L21/82 ,  H01L21/3205 ,  H01L21/8242 ,  H01L23/52 ,  H01L23/522 ,  H01L23/528 ,  H01L27/10 ,  H01L27/108

CPC分类号： H01L23/528 ,  H01L23/5222 ,  H01L2924/0002

摘要： In order to reduce parasitic capacitive cross-coupling in an integrated circuit, metallization lines in an array--for example, an array of word lines, of bit lines, or of bus interconnects--are geometrically arranged in a systematically progressive laterally (sidewise) marching sequence, whereby the identity of the lines located on either side of a given line keeps changing.

摘要翻译： 为了减少集成电路中的寄生电容交叉耦合，阵列中的金属化线（例如字线阵列，位线阵列或总线互连）几何地布置在系统地进行的侧向（侧向）行进 序列，从而位于给定行的任一侧的线的身份不断变化。

公开(公告)号：US5063422A

公开(公告)日：1991-11-05

申请号：US515550

申请日：1990-04-26

申请人： Steven J. Hillenius ,  Joseph Lebowitz ,  Ruichen Liu ,  William T. Lynch

发明人： Steven J. Hillenius ,  Joseph Lebowitz ,  Ruichen Liu ,  William T. Lynch

IPC分类号： H01L21/225 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/08 ,  H01L29/36

CPC分类号： H01L29/0847 ,  H01L21/2257 ,  H01L21/823814 ,  H01L27/0921 ,  H01L29/36 ,  H01L27/0928

摘要： In CMOS based integrated circuits, stricter design rules require source and drain junctions shallower than 2500 .ANG.. By using a specific device configuration, a shallow junction is obtainable while resistance to latch-up is improved and other electrical properties, e.g., low leakage current, are maintained. To achieve this result the p-channel device should have an activation energy of the junction reverse leakage current region less than 1.12 eV, with a junction dopant region shallower than 1200 .ANG. and a monotonically decreasing junction dopant profile.

摘要翻译： 在基于CMOS的集成电路中，更严格的设计规则要求源和漏接点比2500 ANGSTROM浅。 通过使用特定的器件配置，可以获得浅结，同时提高了闩锁的阻力，并且保持了其他电特性，例如低漏电流。 为了实现这一结果，p沟道器件应该具有小于1.12eV的结反向泄漏电流区域的激活能，其中掺杂剂区域比1200安培浅和单调递减的掺杂剂分布。

公开(公告)号：US4694561A

公开(公告)日：1987-09-22

申请号：US676677

申请日：1984-11-30

申请人： Joseph Lebowitz ,  William T. Lynch

发明人： Joseph Lebowitz ,  William T. Lynch

IPC分类号： H01L27/04 ,  G11C11/34 ,  G11C11/403 ,  H01L21/225 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108 ,  H01L29/94 ,  H01L21/72 ,  H01L21/385

CPC分类号： H01L27/10861 ,  H01L21/2257 ,  H01L29/945 ,  Y10S148/109

摘要： A trench version of a high-capacitance (Hi-C) capacitor for a dynamic random-access-memory (DRAM) cell is made utilizing a modified version of the doping technique described in U.S. Pat. No. 4,471,524 and 4,472,212. A shallow highly doped trench region is thereby formed. At the same time, selected lateral surface portions of the structure are also thereby highly doped. These surface portions permit a direct electrical connection to be easily made between the capacitor and a subsequently formed adjacent access transistor.

摘要翻译： 用于动态随机存取存储器（DRAM）单元的高电容（Hi-C）电容器的沟槽版本是利用美国专利No. 第4,471,524和4,472,212号。 由此形成浅的高掺杂沟槽区域。 同时，结构的选定的侧表面部分也因此被高度掺杂。 这些表面部分允许容易地在电容器和随后形成的相邻存取晶体管之间进行直接电连接。

公开(公告)号：US4824796A

公开(公告)日：1989-04-25

申请号：US77953

申请日：1987-07-10

申请人： Tzu-Yin Chiu ,  Gen M. Chin ,  Ronald C. Hanson ,  Maureen Y. Lau ,  Kwing F. Lee ,  Mark D. Morris ,  Alexander M. Voshchenkov ,  Avinoam Kornblit ,  Joseph Lebowitz ,  William T. Lynch

发明人： Tzu-Yin Chiu ,  Gen M. Chin ,  Ronald C. Hanson ,  Maureen Y. Lau ,  Kwing F. Lee ,  Mark D. Morris ,  Alexander M. Voshchenkov ,  Avinoam Kornblit ,  Joseph Lebowitz ,  William T. Lynch

IPC分类号： H01L29/73 ,  H01L21/225 ,  H01L21/3215 ,  H01L21/331 ,  H01L21/82 ,  H01L21/8249 ,  H01L27/06 ,  H01L29/732 ,  H01L21/70 ,  H01L27/00

CPC分类号： H01L29/41783 ,  H01L21/2257 ,  H01L21/32155 ,  H01L21/8249 ,  H01L27/0623 ,  Y10S148/009 ,  Y10S148/01 ,  Y10S148/124 ,  Y10S148/151

摘要： A process for creating bipolar and CMOS transistors on a p-type silicon substrate is disclosed. The silicon substrate has typical n+ buried wells and field oxide regions to isolate the individual transistor devices. In accordance with the process, stacks of material are created over the gate elements of the CMOS devices and over the emitter elements of the bipolar transistors. The stacks of material over the gate elements have a silicon dioxide gate layer in contact with the epitaxial layer of the substrate, and the stacks of material over the emitter elements have a polycrystalline silicon layer in contact with the epitaxial layer. Walls of silicon dioxide are created around the stacks in order to insulate the material within the stacks from the material deposited outside of the walls. Polycrystalline silicon in contact with the epitaxial layer is deposited outside the walls surrounding the stacks. All polycrystalline silicon layers in contact with the epitaxial layer are implanted with appropriate dopants such that these layers serve as reservoirs of dopant in order to simultaneously create the source and drain elements of the CMOS devices and the emitter elements of the bipolar devices during a heating step in the process. A tungsten layer is deposited over the polycrystalline layer in order to provide a conductive coupling to aluminum electrodes.

摘要翻译： 公开了一种在p型硅衬底上制造双极和CMOS晶体管的工艺。 硅衬底具有典型的n +掩埋阱和场氧化物区域以隔离各个晶体管器件。 根据该过程，在CMOS器件的栅极元件和双极晶体管的发射极元件之上形成材料堆叠。 在栅极元件上的堆叠材料具有与衬底的外延层接触的二氧化硅栅极层，并且在发射极元件上的材料堆叠具有与外延层接触的多晶硅层。 在堆叠周围产生二氧化硅壁，以便将堆叠内的材料与沉积在壁外部的材料隔离。 与外延层接触的多晶硅沉积在堆叠周围的壁的外部。 与外延层接触的所有多晶硅层都注入合适的掺杂剂，使得这些层用作掺杂剂的储存器，以便在加热步骤期间同时产生CMOS器件的源极和漏极元件以及双极器件的发射极元件 正在进行中。 为了提供与铝电极的导电耦合，在多晶层上沉积钨层。

公开(公告)号：US06459949B1

公开(公告)日：2002-10-01

申请号：US09176537

申请日：1998-10-21

申请人： Hang T. Black ,  Arturo N. Morosoff ,  Joseph Lebowitz

发明人： Hang T. Black ,  Arturo N. Morosoff ,  Joseph Lebowitz

IPC分类号： G06F1900

CPC分类号： G05B19/41875 ,  G05B2219/31365 ,  G05B2219/32214 ,  Y02P90/12 ,  Y02P90/22 ,  Y10S707/99945 ,  Y10S707/99948 ,  Y10S707/99953

摘要： A system and method for recording and addressing out of control (OOC) events in a semiconductor processing line. The method includes steps of (a) opening OOC entries in an OOC database, and (b) working the OOC entries. Opening an OOC entry is performed in response to one or more OOC events in wafer lots being processed in the semiconductor processing line. A lot record addresses an isolated occurrence pertaining to one wafer lot. An issue record addresses a trend of repeated defects or failures. Opening an OOC entry in the OOC database preferably includes assigning and recording an “owner” responsible for addressing the OOC entry. Working the OOC entries includes opening activity records for the OOC entries, receiving user input on corrective measures, and recording the measures in the activity records. The method preferably also includes steps of (c) closing OOC entries after working the OOC entries, and (d) reassigning OOC entries if ownership is transferred for the entries. The system includes (a) a plurality of computer systems, including a plurality of entry terminals, (b) an OOC database coupled to the plurality of computer systems, (c) an OOC interface executing on one or more of the entry terminals and coupled to the OOC database, and (d) an OOC tracking program executing on one or more of the computer systems and coupled to the OOC database and to the OOC interface.

摘要翻译： 一种用于在半导体处理线中记录和寻址失控（OOC）事件的系统和方法。 该方法包括以下步骤：（a）在OOC数据库中打开OOC条目，以及（b）处理OOC条目。 响应于在半导体处理线中处理的晶片批次中的一个或多个OOC事件来执行打开OOC条目。 许多记录解决了与一个晶圆批次有关的孤立事件。 问题记录解决了重复缺陷或失败的趋势。 在OOC数据库中打开OOC条目最好包括分配和记录负责处理OOC条目的“所有者”。 工作OOC条目包括打开OOC条目的活动记录，接收用户对纠正措施的输入，并将措施记录在活动记录中。 该方法优选还包括（c）在工作OOC条目之后关闭OOC条目的步骤，以及（d）如果所有权转移给条目，则重新分配OOC条目。 该系统包括（a）多个计算机系统，包括多个入口终端，（b）耦合到多个计算机系统的OOC数据库，（c）在一个或多个入口终端上执行的OOC接口， 到OOC数据库，以及（d）在一个或多个计算机系统上执行的OOC跟踪程序，并且耦合到OOC数据库和OOC接口。

公开(公告)号：US06328905B1

公开(公告)日：2001-12-11

申请号：US09372895

申请日：1999-08-12

申请人： Joseph Lebowitz ,  Laura E. Faulk

发明人： Joseph Lebowitz ,  Laura E. Faulk

IPC分类号： C23F100

CPC分类号： H01L21/02054 ,  G03F7/423 ,  H01L21/02063 ,  H01L21/76838

摘要： Methods of removing resist residues from semiconductor workpiece surfaces are provided. In one aspect, a method of removing resist from a surface of a workpiece is provided that includes the steps of exposing the workpiece to a plasma and rinsing the workpiece with CO2 and water in a processing chamber to dissolve the resist. Reliance on post plasma strip solvent rinses for resist removal is eliminated. The combination of CO2 with post-plasma strip water rinse increases the solubility and thus the removal rate of resist residues.

摘要翻译： 提供了从半导体工件表面去除抗蚀剂残留物的方法。 一方面，提供从工件表面去除抗蚀剂的方法，其包括将工件暴露于等离子体并用处理室中的CO 2和水冲洗工件以溶解抗蚀剂的步骤。 消除了后置等离子体条的溶剂冲洗，以抵抗抗蚀剂去除。 CO2与后等离子体条带水冲洗的组合增加了抗蚀剂残留物的溶解度和去除速率。

公开(公告)号：US4653177A

公开(公告)日：1987-03-31

申请号：US758717

申请日：1985-07-25

申请人： Joseph Lebowitz ,  Thomas E. Seidel

发明人： Joseph Lebowitz ,  Thomas E. Seidel

IPC分类号： H01L21/76 ,  H01L21/033 ,  H01L21/265 ,  H01L21/316 ,  H01L21/762 ,  H01L21/822 ,  H01L27/04 ,  H01L27/08 ,  H01L21/78

CPC分类号： H01L21/31654 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/76237

摘要： It is known to utilize dielectric-filled trenches in a CMOS integrated-circuit device to achieve electrical isolation between adjacent n-channel and p-channel regions. In that way, latchup-free operation of the device is ensured. But inversion effects along the walls of the trenches can cause high leakage currents, undesirably high parasitic capacitances and even shorting together of source/drain regions. In accordance with the invention, a nonlithographic technique including selective anodic oxidation is employed to selectively mask the sidewalls of the trenches. Each sidewall can then be independently doped thereby effectively eliminating the possibility of inversion occurring therealong.

摘要翻译： 已知在CMOS集成电路器件中使用介质填充的沟槽来实现相邻的n沟道和p沟道区之间的电隔离。 以这种方式，确保了设备的无闩锁操作。 但是沿着沟槽的壁的反向效应可能导致高漏电流，不期望的高寄生电容，甚至源/漏区的一起短路。 根据本发明，采用包括选择性阳极氧化的非光刻技术来选择性地掩蔽沟槽的侧壁。 然后每个侧壁可以被独立地掺杂，从而有效地消除了沿着它发生反转的可能性。