公开(公告)号：US20130284500A1

公开(公告)日：2013-10-31

申请号：US13455364

申请日：2012-04-25

申请人： Jun-Chung Hsu ,  Chi-Ming Lin ,  Tso-Hung Yeh ,  Ya-Hsiang Chen

发明人： Jun-Chung Hsu ,  Chi-Ming Lin ,  Tso-Hung Yeh ,  Ya-Hsiang Chen

IPC分类号： H05K1/03 ,  H05K1/02

CPC分类号： H05K3/388 ,  H05K3/381 ,  H05K2203/0307

摘要： A laminate circuit board structure from button up including a substrate, a circuit metal layer, a nanometer plating layer and a cover layer is disclosed. The nanometer plating layer is smooth a thickness of 5-40 nm, and can be directly forming on the outer surface of the circuit metal layer or manufactured by firstly forming the nanometer plating layer on a preforming substrate, then pressing the substrate against the nanometer plating layer, and finally removing the preforming substrate. The junction adhesion between the nanometer plating layer and the cover layer or the substrate is improved by chemical bonding. Therefore it does not need to roughen the circuit metal layer or reserve circuit width for compensation such that the density of the circuit increases and much more dense circuit can be implemented in the substrate with the same area.

摘要翻译： 公开了一种按钮的层叠电路板结构，包括基板，电路金属层，纳米电镀层和覆盖层。 纳米电镀层的光滑厚度为5-40nm，可以直接形成在电路金属层的外表面上，或者通过首先在预成型基板上形成纳米镀层，然后将衬底压在纳米电镀上 层，最后除去预成型基板。 通过化学键合可以改善纳米镀层与覆盖层或衬底之间的结合性。 因此，不需要粗糙化电路金属层或补偿电路宽度，使得电路的密度增加，并且可以在具有相同面积的基板中实现更加密集的电路。

公开(公告)号：US20130255858A1

公开(公告)日：2013-10-03

申请号：US13437933

申请日：2012-04-03

申请人： Jun-Chung Hsu ,  Chi-Ming Lin ,  Tso-Hung Yeh ,  Ya-Hsiang Chen

发明人： Jun-Chung Hsu ,  Chi-Ming Lin ,  Tso-Hung Yeh ,  Ya-Hsiang Chen

IPC分类号： B32B38/10 ,  B32B38/08

CPC分类号： H05K3/282 ,  H05K1/0366 ,  H05K3/103 ,  H05K3/146 ,  H05K3/16 ,  H05K3/202 ,  H05K3/244 ,  H05K3/381 ,  H05K3/384 ,  H05K2201/0376 ,  H05K2201/09227 ,  H05K2203/0152 ,  H05K2203/0278 ,  H05K2203/072 ,  Y10T156/10

摘要： A method of manufacturing a laminate circuit board is disclosed. The method includes forming a metal layer on a substrate, patterning the metal layer to form a circuit metal layer, forming a nanometer plating layer with a thickness of 5 to 40 nm over the circuit metal layer, and forming a cover layer covering the substrate and the nanometer plating layer with improved adhesion by chemical bonding to form the laminate circuit board. Another method includes forming the circuit metal layer and the nanometer plating layer on a preforming substrate, pressing the preforming substrate against a substrate to push the circuit metal layer and the nanometer plating layer into the substrate, and removing the preforming substrate. By the present invention, the density of circuit is increased and much denser circuit can be implemented on the substrate with the same area.

摘要翻译： 公开了一种制造叠层电路板的方法。 该方法包括在基板上形成金属层，图案化金属层以形成电路金属层，在电路金属层上形成厚度为5至40nm的纳米电镀层，并形成覆盖基板的覆盖层和 纳米电镀层通过化学键合具有改善的粘附性以形成层压电路板。 另一种方法包括在预成型基板上形成电路金属层和纳米电镀层，将预成型基板压靠在基板上，将电路金属层和纳米电镀层推入基板，以及去除预成形基板。 通过本发明，电路的密度增加，并且可以在具有相同面积的基板上实现更加密集的电路。

公开(公告)号：US20100309608A1

公开(公告)日：2010-12-09

申请号：US12479810

申请日：2009-06-07

申请人： Chien-Wei Chang ,  Ting-Hao Lin ,  Ya-Hsiang Chen ,  Yu-Te Lu

发明人： Chien-Wei Chang ,  Ting-Hao Lin ,  Ya-Hsiang Chen ,  Yu-Te Lu

IPC分类号： H01M6/14

CPC分类号： H01G4/01 ,  H01G4/005 ,  H01G4/06 ,  H01G4/228

摘要： A buried capacitor structure including a first conductive metal layer, a first dielectric film, a capacitor, a second dielectric film, and a second conductive metal layer, which are stacked in sequence, wherein the capacitor is buried between the first dielectric film and the second dielectric film, the first conductive metal layer is formed into a first circuit pattern, the second conductive metal layer is formed into a second circuit pattern. The capacitor is a planar comb-shaped capacitor with a positive electrode, a negative electrode, and a capacitor paste filled between the positive electrode and the negative electrode, wherein the positive electrode includes a positive electrode end and a plurality of positive comb branches, the negative electrode includes a negative electrode end and a plurality of negative comb branches, and the positive branches and the negative branches are parallel to and separated from each other.

摘要翻译： 一种埋置电容器结构，其包括依次层叠的第一导电金属层，第一电介质膜，电容器，第二电介质膜和第二导电金属层，其中，所述电容器埋设在所述第一电介质膜和所述第二电介质膜之间 电介质膜，第一导电金属层形成为第一电路图案，第二导电金属层形成第二电路图案。 电容器是具有正极，负极和填充在正极和负极之间的电容器浆料的平面梳状电容器，其中正极包括正极端和多个正梳分支， 负极包括负极端和多个负梳分支，并且正分支和负分支彼此平行并分离。

公开(公告)号：US08377815B2

公开(公告)日：2013-02-19

申请号：US13043463

申请日：2011-03-09

申请人： Chien-Wei Chang ,  Ting-Hao Lin ,  Ya-Hsiang Chen

发明人： Chien-Wei Chang ,  Ting-Hao Lin ,  Ya-Hsiang Chen

IPC分类号： H01L21/44

CPC分类号： H01L24/13 ,  H01L21/4853 ,  H01L23/49811 ,  H01L24/11 ,  H01L2224/1147 ,  H01L2224/11903 ,  H01L2224/13022 ,  H01L2224/13076 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/13611 ,  H01L2224/13655 ,  H01L2924/01029 ,  H01L2924/12042 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/01079 ,  H01L2924/00

摘要： A manufacturing method of a semiconductor load board is disclosed. The manufacturing method includes a first conductive layer forming step, a first patterning step, a dielectric layer forming step, a drilling step, a second conductive layer forming step, a second patterning step or a two-times patterning step, and a solder connecting step. In a second patterning step or a two-times patterning step, a solder pad is formed in the opening of the dielectric layer, wherein each solder pad has a height higher than the height of the dielectric, and the width of each solder pad is equal to or smaller than the maximum width of the opening, such that wider intervals are provided in the same area and the problems of short circuit failure and electrical interference can be reduced.

摘要翻译： 公开了一种半导体负载板的制造方法。 该制造方法包括第一导电层形成步骤，第一图案化步骤，介电层形成步骤，钻孔步骤，第二导电层形成步骤，第二图案化步骤或两次图案化步骤，以及焊料连接步骤 。 在第二图案化步骤或二次图案化步骤中，在电介质层的开口中形成焊料焊盘，其中每个焊盘的高度高于电介质的高度，并且每个焊盘的宽度相等 达到或小于开口的最大宽度，使得在相同的区域中设置更宽的间隔，并且可以减少短路故障和电气干扰的问题。

公开(公告)号：US08312624B1

公开(公告)日：2012-11-20

申请号：US13304340

申请日：2011-11-24

申请人： Chien-Wei Chang ,  Ting-Hao Lin ,  Ya-Hsiang Chen ,  De-Hao Lu

发明人： Chien-Wei Chang ,  Ting-Hao Lin ,  Ya-Hsiang Chen ,  De-Hao Lu

IPC分类号： H05K3/02

CPC分类号： H05K3/427 ,  H05K1/0206 ,  H05K3/421 ,  H05K2203/025 ,  H05K2203/0733 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49165

摘要： A method for manufacturing a heat dissipation structure of a printed circuit board includes: forming a barrier layer on the dimple in the first copper plating layer; forming a nickel plating layer; removing the nickel plating layer and the barrier layer on the dimple; forming a second copper plating layer to make the total height of the first copper plating layer and the second copper plating layer in the second opening higher than that of the first copper plating layer in the first opening; filling the dimple in the second copper plating layer with an etching-resistant material; removing the second copper plating layer; removing the nickel plating layer and the etching-resistant material to make the second copper plating layer in the second opening being at the same height as the first copper plating layer in the first opening; and forming the heat dissipation structure by photolithography.

摘要翻译： 制造印刷电路板的散热结构的方法包括：在第一镀铜层的凹坑上形成阻挡层; 形成镀镍层; 去除凹坑上的镀镍层和阻挡层; 形成第二镀铜层，使第二开口中的第一镀铜层和第二镀铜层的总高度高于第一开口中的第一镀铜层的总高度; 用耐腐蚀材料填充第二镀铜层中的凹坑; 去除所述第二镀铜层; 去除镀镍层和耐腐蚀材料，使得第二开口中的第二镀铜层处于与第一开口中的第一铜镀层相同的高度; 并通过光刻法形成散热结构。

公开(公告)号：US20120231621A1

公开(公告)日：2012-09-13

申请号：US13043463

申请日：2011-03-09

申请人： Chien-Wei Chang ,  Ting-Hao Lin ,  Ya-Hsiang Chen

发明人： Chien-Wei Chang ,  Ting-Hao Lin ,  Ya-Hsiang Chen

IPC分类号： H01L21/28

CPC分类号： H01L24/13 ,  H01L21/4853 ,  H01L23/49811 ,  H01L24/11 ,  H01L2224/1147 ,  H01L2224/11903 ,  H01L2224/13022 ,  H01L2224/13076 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/13611 ,  H01L2224/13655 ,  H01L2924/01029 ,  H01L2924/12042 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/01079 ,  H01L2924/00

摘要： A manufacturing method of a semiconductor load board is disclosed. The manufacturing method includes a first conductive layer forming step, a first patterning step, a dielectric layer forming step, a drilling step, a second conductive layer forming step, a second patterning step or a two-times patterning step, and a solder connecting step. In a second patterning step or a two-times patterning step, a solder pads is formed in the opening of the dielectric layer, wherein each solder pad has a height higher than the height of the dielectric, and the width of each solder pad is equal to or smaller than the maximum width of the opening, such that wider intervals are provided in the same area and the problems of short circuit failure and electrical interference can be reduced.

摘要翻译： 公开了一种半导体负载板的制造方法。 该制造方法包括第一导电层形成步骤，第一图案化步骤，介电层形成步骤，钻孔步骤，第二导电层形成步骤，第二图案化步骤或两次图案化步骤，以及焊料连接步骤 。 在第二图案化步骤或两次图案化步骤中，在电介质层的开口中形成焊盘，其中每个焊盘的高度高于电介质的高度，并且每个焊垫的宽度相等 达到或小于开口的最大宽度，使得在相同的区域中设置更宽的间隔，并且可以减少短路故障和电气干扰的问题。

公开(公告)号：US07871892B2

公开(公告)日：2011-01-18

申请号：US12479811

申请日：2009-06-07

申请人： Chien-Wei Chang ,  Ting-Hao Lin ,  Ya-Hsiang Chen ,  Yu-Te Lu

发明人： Chien-Wei Chang ,  Ting-Hao Lin ,  Ya-Hsiang Chen ,  Yu-Te Lu

IPC分类号： H01L21/20

CPC分类号： B32B37/02 ,  B32B38/06 ,  B32B2038/047 ,  B32B2457/08 ,  B32B2457/16 ,  H01G4/236 ,  H01G4/33 ,  H05K1/162 ,  H05K3/4602 ,  H05K2201/09236 ,  H05K2201/09509 ,  H05K2203/1461

摘要： A method for fabricating a buried capacitor structure includes: laminating a first dielectric layer having a capacitor embedded therein with a second dielectric layer to bury the capacitor therebetween; forming a first circuit pattern on a first metal layer of the first dielectric layer and a second circuit pattern on a second metal layer of the second dielectric layer; depositing a first insulating layer and a second insulating layer on the first metal layer and the second metal layer, respectively; electrically connecting a positive electrode end and a negative electrode end of the capacitor to the second metal layer by a positive through-hole and a negative through-hole, thereby manufacturing the buried capacitor structure.

摘要翻译： 一种埋入式电容器结构的制造方法，其特征在于：将具有嵌入其中的电容器的第一电介质层与第二电介质层层叠， 在所述第一介电层的第一金属层上形成第一电路图案，在所述第二介电层的第二金属层上形成第二电路图案; 分别在第一金属层和第二金属层上沉积第一绝缘层和第二绝缘层; 通过正通孔和负通孔将电容器的正极端子和负极端子电连接到第二金属层，从而制造埋入式电容器结构。

公开(公告)号：US20120228011A1

公开(公告)日：2012-09-13

申请号：US13043462

申请日：2011-03-09

申请人： Chien-Wei Chang ,  Ting-Hao Lin ,  Ya-Hsiang Chen

发明人： Chien-Wei Chang ,  Ting-Hao Lin ,  Ya-Hsiang Chen

IPC分类号： H05K1/09 ,  H05K1/00

CPC分类号： H01L23/49816 ,  H01L24/13 ,  H01L2224/0401 ,  H01L2224/05567 ,  H01L2224/13007 ,  H01L2224/13022 ,  H01L2224/13076 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/014 ,  H05K3/4007 ,  H05K2201/0367 ,  H01L2224/05552

摘要： Disclosed is a semiconductor load board, including a substrate, a plurality of connection pads, a patterned circuit layer, a dielectric layer, a plurality of solder pads, and a plurality of solders. The connection pads and the patterned circuit layer are located on the substrate. The dielectric layer is formed on the substrate, the connection pads and the patterned circuit layer, and has a plurality of openings corresponding to the plurality of connection pads. The solder pads are formed in the openings, and the width of the solder pads is smaller than or equals to the maximum width of the openings of the dielectric layer, and a protruding portion which has a width smaller than the minimum width of the openings of the dielectric layer can also be formed, such that the problems of short-circuit failure and electrical interference can be reduced.

摘要翻译： 公开了一种半导体负载板，包括基板，多个连接焊盘，图案化电路层，电介质层，多个焊盘和多个焊料。 连接焊盘和图案化电路层位于衬底上。 介电层形成在基板上，连接焊盘和图案化电路层上，并且具有对应于多个连接焊盘的多个开口。 焊盘形成在开口中，并且焊盘的宽度小于或等于电介质层的开口的最大宽度，并且宽度小于开口的最小宽度的突出部分 还可以形成电介质层，从而可以减少短路故障和电气干扰的问题。

公开(公告)号：US20100307666A1

公开(公告)日：2010-12-09

申请号：US12479811

申请日：2009-06-07

申请人： Chien-Wei Chang ,  Ting-Hao Lin ,  Ya-Hsiang Chen ,  Yu-Te Lu

发明人： Chien-Wei Chang ,  Ting-Hao Lin ,  Ya-Hsiang Chen ,  Yu-Te Lu

IPC分类号： B32B37/00

CPC分类号： B32B37/02 ,  B32B38/06 ,  B32B2038/047 ,  B32B2457/08 ,  B32B2457/16 ,  H01G4/236 ,  H01G4/33 ,  H05K1/162 ,  H05K3/4602 ,  H05K2201/09236 ,  H05K2201/09509 ,  H05K2203/1461

摘要： A method for fabricating a buried capacitor structure includes: laminating a first dielectric layer having a capacitor embedded therein with a second dielectric layer to bury the capacitor therebetween; forming a first circuit pattern on a first metal layer of the first dielectric layer and a second circuit pattern on a second metal layer of the second dielectric layer; depositing a first insulating layer and a second insulating layer on the first metal layer and the second metal layer, respectively; electrically connecting a positive electrode end and a negative electrode end of the capacitor to the second metal layer by a positive through-hole and a negative through-hole, thereby manufacturing the buried capacitor structure.

摘要翻译： 一种埋入式电容器结构的制造方法，其特征在于：将具有嵌入其中的电容器的第一电介质层与第二电介质层层叠， 在所述第一介电层的第一金属层上形成第一电路图案，在所述第二介电层的第二金属层上形成第二电路图案; 分别在第一金属层和第二金属层上沉积第一绝缘层和第二绝缘层; 通过正通孔和负通孔将电容器的正极端子和负极端子电连接到第二金属层，从而制造埋入式电容器结构。