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    Method for forming a multi-layered structure of a semiconductor device and methods for forming a capacitor and a gate insulation layer using the multi-layered structure
    3.
    发明授权
    Method for forming a multi-layered structure of a semiconductor device and methods for forming a capacitor and a gate insulation layer using the multi-layered structure 失效
    用于形成半导体器件的多层结构的方法以及使用该多层结构形成电容器和栅极绝缘层的方法

    公开(公告)号：US06989338B2

    公开(公告)日：2006-01-24

    申请号：US10737394

    申请日：2003-12-15

    申请人： Han-Mei Choi ,  Young-Wook Park ,  Eun-Taek Yim ,  Dong-Jo Kang ,  Kyoung-Seok Kim

    发明人： Han-Mei Choi ,  Young-Wook Park ,  Eun-Taek Yim ,  Dong-Jo Kang ,  Kyoung-Seok Kim

    IPC分类号： H01L21/26

    CPC分类号： H01L21/28194 ,  H01L29/513 ,  H01L29/517

    摘要： Disclosed is a method for forming a multi-layered structure having at least two films on a semiconductor substrate. The substrate is disposed on a thermally conductible stage for supporting the substrate. After the distance between the stage and the substrate is adjusted to a first interval so that the substrate has a first temperature by heat transferred from the stage, a first thin film is formed on the substrate at the first temperature. The distance is then adjusted from the first interval to a second interval so that the substrate reaches a second temperature, and then a second thin film is formed on the first thin film at the second temperature, thereby forming the multi-layered structure on the substrate. The multi-layered structure can be employed for a gate insulation film or the dielectric film of a capacitor.

    摘要翻译： 公开了一种在半导体衬底上形成至少具有两个膜的多层结构的方法。 基板设置在用于支撑基板的导热性台上。 在阶段和衬底之间的距离被调整到第一间隔，使得衬底具有通过从载物台传递的热量的第一温度，在第一温度下在衬底上形成第一薄膜。 然后将距离从第一间隔调整到第二间隔，使得衬底达到第二温度，然后在第二温度下在第一薄膜上形成第二薄膜，从而在衬底上形成多层结构 。 多层结构可以用于栅极绝缘膜或电容器的电介质膜。

    Method of manufacturing a semiconductor device including alignment mark
    4.
    发明授权
    Method of manufacturing a semiconductor device including alignment mark 有权
    制造包括对准标记的半导体器件的方法

    公开(公告)号：US06794263B1

    公开(公告)日：2004-09-21

    申请号：US10367931

    申请日：2003-02-19

    申请人： Kong-Soo Lee ,  Young-Wook Park ,  Jae-Jong Han ,  Gi-Hyun Hwang ,  Kyoung-Seok Kim ,  Sung-Eui Kim ,  Seung-Mok Shin

    发明人： Kong-Soo Lee ,  Young-Wook Park ,  Jae-Jong Han ,  Gi-Hyun Hwang ,  Kyoung-Seok Kim ,  Sung-Eui Kim ,  Seung-Mok Shin

    IPC分类号： H01L2176

    CPC分类号： H01L23/544 ,  G03F9/7076 ,  G03F9/708 ,  G03F9/7084 ,  H01L21/76229 ,  H01L2223/54453 ,  H01L2924/0002 ,  Y10S438/959 ,  Y10S438/975 ,  H01L2924/00

    摘要： A method of inhibiting pit occurrence on a semiconductor substrate during manufacture of a semiconductor device includes forming an isolation using a shallow trench isolation (STI) method in a semiconductor substrate, forming an insulation layer on an entire surface of the semiconductor substrate having the isolation, implanting ions into the semiconductor substrate using the insulation layer as a buffer layer, annealing the semiconductor substrate using a rapid thermal annealing (RTA) process, forming a photoresist layer on the insulation layer and then forming an opening in the photoresist layer to expose an underlayer thereof, forming an align key by etching the underlayer at the opening, and removing the photoresist layer and the insulation layer. Alternatively, the thickness of the insulation layer may be reduced to prevent the occurrence of pits on active areas of the semiconductor substrate.

    摘要翻译： 在半导体器件的制造期间抑制半导体衬底上的凹坑产生的方法包括在半导体衬底中形成使用浅沟槽隔离（STI）方法的隔离，在具有隔离的半导体衬底的整个表面上形成绝缘层， 使用绝缘层作为缓冲层将离子注入到半导体衬底中，使用快速热退火（RTA）工艺对半导体衬底进行退火，在绝缘层上形成光致抗蚀剂层，然后在光刻胶层中形成开口以暴露底层 通过在开口处蚀刻底层形成对准键，以及去除光致抗蚀剂层和绝缘层。 或者，可以减小绝缘层的厚度，以防止在半导体衬底的有源区域上出现凹坑。

    Stacked semiconductor devices and methods of manufacturing the same
    5.
    发明授权
    Stacked semiconductor devices and methods of manufacturing the same 失效
    叠层半导体器件及其制造方法

    公开(公告)号：US08039900B2

    公开(公告)日：2011-10-18

    申请号：US11823765

    申请日：2007-06-28

    申请人： Kyoung-Seok Kim ,  Kong-Soo Lee ,  Sang-Jin Park ,  Sung-Kwan Kang ,  Ko-Eun Lee

    发明人： Kyoung-Seok Kim ,  Kong-Soo Lee ,  Sang-Jin Park ,  Sung-Kwan Kang ,  Ko-Eun Lee

    IPC分类号： H01L29/66

    CPC分类号： H01L27/0688 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02636 ,  H01L21/28556 ,  H01L21/76879 ,  H01L21/76898 ,  H01L21/8221 ,  H01L27/11 ,  H01L27/1104 ,  H01L27/1108

    摘要： The stacked semiconductor device includes a semiconductor substrate, a multi-layered insulation layer pattern having at least two insulation layer patterns and an opening, an active layer pattern formed on each of the insulation layer patterns, a first plug including single crystalline silicon-germanium, a second plug including single crystalline silicon, and a wiring electrically connected to the first plug and sufficiently filling up the opening. The insulation layer patterns are vertically stacked on the semiconductor substrate and the opening exposes an upper face of the semiconductor substrate. A side portion of the active layer pattern is exposed by the opening. The first plug is formed on the upper face of the semiconductor substrate to partially fill the opening. The second plug is partially formed on the first plug, and has substantially the same interface as that of the first plug.

    摘要翻译： 叠层半导体器件包括半导体衬底，具有至少两个绝缘层图案和开口的多层绝缘层图案，形成在每个绝缘层图案上的有源层图案，包括单晶硅锗的第一插头， 包括单晶硅的第二插头和电连接到第一插头并充分填满开口的布线。 绝缘层图案垂直堆叠在半导体衬底上，并且开口暴露半导体衬底的上表面。 有源层图案的侧面部分由开口露出。 第一插头形成在半导体衬底的上表面上以部分地填充开口。 第二插头部分地形成在第一插头上，并且具有与第一插头基本相同的界面。

    Methods of forming integrated circuit devices having vertical semiconductor interconnects and diodes therein and devices formed thereby
    6.
    发明授权
    Methods of forming integrated circuit devices having vertical semiconductor interconnects and diodes therein and devices formed thereby 有权
    形成其中具有垂直半导体互连和二极管的集成电路器件的方法及由此形成的器件

    公开(公告)号：US08119503B2

    公开(公告)日：2012-02-21

    申请号：US12498528

    申请日：2009-07-07

    申请人： Kong-Soo Lee ,  Kyoung-Seok Kim ,  Sang-Jin Park ,  Chang-Hoon Lee ,  Ji-Hyun Jeong ,  Jae-Hyun Park ,  Jae-Hee Oh

    发明人： Kong-Soo Lee ,  Kyoung-Seok Kim ,  Sang-Jin Park ,  Chang-Hoon Lee ,  Ji-Hyun Jeong ,  Jae-Hyun Park ,  Jae-Hee Oh

    IPC分类号： H01L47/00 ,  H01L21/20

    CPC分类号： H01L27/1021 ,  H01L27/24 ,  H01L29/8613

    摘要： Methods of forming integrated circuit devices include forming an etch stop layer on a surface of a semiconductor substrate and forming a first interlayer insulating layer on the etch stop layer. The first interlayer insulating layer is patterned to define an opening therein that exposes a first portion of the etch stop layer. This first portion of the etch stop layer is then removed to thereby expose an underlying portion of the surface of the semiconductor substrate. This removal of the etch stop layer may be performed by wet etching the first portion of the etch stop layer using a phosphoric acid solution. A semiconductor region is then selectively grown into the opening, using the exposed portion of the surface of the semiconductor substrate as an epitaxial seed layer.

    摘要翻译： 形成集成电路器件的方法包括在半导体衬底的表面上形成蚀刻停止层，并在蚀刻停止层上形成第一层间绝缘层。 图案化第一层间绝缘层以限定其中暴露出蚀刻停止层的第一部分的开口。 然后去除蚀刻停止层的第一部分，从而暴露半导体衬底的表面的下面部分。 蚀刻停止层的这种去除可以通过使用磷酸溶液湿蚀刻蚀刻停止层的第一部分来进行。 然后使用半导体衬底的表面的暴露部分作为外延种子层，选择性地将半导体区域生长到开口中。

    Methods of Forming Integrated Circuit Devices Having Vertical Semiconductor Interconnects and Diodes Therein and Devices Formed Thereby
    7.
    发明申请
    Methods of Forming Integrated Circuit Devices Having Vertical Semiconductor Interconnects and Diodes Therein and Devices Formed Thereby 有权
    形成具有垂直半导体互连和二极管的集成电路器件的方法和由此形成的器件

    公开(公告)号：US20100108971A1

    公开(公告)日：2010-05-06

    申请号：US12498528

    申请日：2009-07-07

    申请人： Kong-Soo Lee ,  Kyoung-Seok Kim ,  Sang-Jin Park ,  Chang-Hoon Lee ,  Ji-Hyun Jeong ,  Jae-Hyun Park ,  Jae-Hee Oh

    发明人： Kong-Soo Lee ,  Kyoung-Seok Kim ,  Sang-Jin Park ,  Chang-Hoon Lee ,  Ji-Hyun Jeong ,  Jae-Hyun Park ,  Jae-Hee Oh

    IPC分类号： H01L47/00 ,  H01L21/20

    CPC分类号： H01L27/1021 ,  H01L27/24 ,  H01L29/8613

    摘要： Methods of forming integrated circuit devices include forming an etch stop layer on a surface of a semiconductor substrate and forming a first interlayer insulating layer on the etch stop layer. The first interlayer insulating layer is patterned to define an opening therein that exposes a first portion of the etch stop layer. This first portion of the etch stop layer is then removed to thereby expose an underlying portion of the surface of the semiconductor substrate. This removal of the etch stop layer may be performed by wet etching the first portion of the etch stop layer using a phosphoric acid solution. A semiconductor region is then selectively grown into the opening, using the exposed portion of the surface of the semiconductor substrate as an epitaxial seed layer.

    摘要翻译： 形成集成电路器件的方法包括在半导体衬底的表面上形成蚀刻停止层，并在蚀刻停止层上形成第一层间绝缘层。 图案化第一层间绝缘层以限定其中暴露出蚀刻停止层的第一部分的开口。 然后去除蚀刻停止层的第一部分，从而暴露半导体衬底的表面的下面部分。 蚀刻停止层的这种去除可以通过使用磷酸溶液湿蚀刻蚀刻停止层的第一部分来进行。 然后使用半导体衬底的表面的暴露部分作为外延种子层，选择性地将半导体区域生长到开口中。