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    Method for forming a multi-layered structure of a semiconductor device and methods for forming a capacitor and a gate insulation layer using the multi-layered structure
    3.
    发明授权
    Method for forming a multi-layered structure of a semiconductor device and methods for forming a capacitor and a gate insulation layer using the multi-layered structure 失效
    用于形成半导体器件的多层结构的方法以及使用该多层结构形成电容器和栅极绝缘层的方法

    公开(公告)号：US06989338B2

    公开(公告)日：2006-01-24

    申请号：US10737394

    申请日：2003-12-15

    申请人： Han-Mei Choi ,  Young-Wook Park ,  Eun-Taek Yim ,  Dong-Jo Kang ,  Kyoung-Seok Kim

    发明人： Han-Mei Choi ,  Young-Wook Park ,  Eun-Taek Yim ,  Dong-Jo Kang ,  Kyoung-Seok Kim

    IPC分类号： H01L21/26

    CPC分类号： H01L21/28194 ,  H01L29/513 ,  H01L29/517

    摘要： Disclosed is a method for forming a multi-layered structure having at least two films on a semiconductor substrate. The substrate is disposed on a thermally conductible stage for supporting the substrate. After the distance between the stage and the substrate is adjusted to a first interval so that the substrate has a first temperature by heat transferred from the stage, a first thin film is formed on the substrate at the first temperature. The distance is then adjusted from the first interval to a second interval so that the substrate reaches a second temperature, and then a second thin film is formed on the first thin film at the second temperature, thereby forming the multi-layered structure on the substrate. The multi-layered structure can be employed for a gate insulation film or the dielectric film of a capacitor.

    摘要翻译： 公开了一种在半导体衬底上形成至少具有两个膜的多层结构的方法。 基板设置在用于支撑基板的导热性台上。 在阶段和衬底之间的距离被调整到第一间隔，使得衬底具有通过从载物台传递的热量的第一温度，在第一温度下在衬底上形成第一薄膜。 然后将距离从第一间隔调整到第二间隔，使得衬底达到第二温度，然后在第二温度下在第一薄膜上形成第二薄膜，从而在衬底上形成多层结构 。 多层结构可以用于栅极绝缘膜或电容器的电介质膜。

    Method of forming a thin layer structure
    6.
    发明授权
    Method of forming a thin layer structure 有权
    形成薄层结构的方法

    公开(公告)号：US08492251B2

    公开(公告)日：2013-07-23

    申请号：US13596339

    申请日：2012-08-28

    申请人： Jong-Hoon Kang ,  Bong-Jin Kuh ,  Tae-Gon Kim ,  Han-Mei Choi ,  Ki-Chul Kim ,  Eun-Young Jo

    发明人： Jong-Hoon Kang ,  Bong-Jin Kuh ,  Tae-Gon Kim ,  Han-Mei Choi ,  Ki-Chul Kim ,  Eun-Young Jo

    IPC分类号： H01L21/20

    CPC分类号： H01L21/02433 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/268 ,  H01L21/324 ,  H01L29/045

    摘要： A thin layer structure includes a substrate, a blocking pattern that exposes part of an upper surface of the substrate, and a single crystalline semiconductor layer on the part of the upper surface of the substrate exposed by the pattern and in which all outer surfaces of the single crystalline semiconductor layer have a crystallographic orientation. The thin layer structure is formed by an SEG process in which the temperature is controlled to prevent migration of atoms in directions towards the central portion of the upper surface of the substrate. Thus, sidewall surfaces of the layer will not be constituted by facets.

    摘要翻译： 薄层结构包括衬底，暴露衬底的上表面的一部分的阻挡图案以及在衬底的上表面部分上的单晶半导体层，其中所述衬底的所有外表面 单晶半导体层具有<100>晶体取向。 薄层结构由SEG工艺形成，其中控制温度以防止原子沿着朝向衬底上表面的中心部分的方向迁移。 因此，该层的侧壁表面将不由小平面构成。

    Semiconductor device and gate structure having a composite dielectric layer and methods of manufacturing the same
    8.
    发明授权
    Semiconductor device and gate structure having a composite dielectric layer and methods of manufacturing the same 有权
    具有复合介质层的半导体器件和栅极结构及其制造方法

    公开(公告)号：US07888727B2

    公开(公告)日：2011-02-15

    申请号：US12457364

    申请日：2009-06-09

    申请人： Ki-Yeon Park ,  Kyoung-Ryul Yoon ,  Dae-Sik Choi ,  Han-Mei Choi ,  Seung-Hwan Lee

    发明人： Ki-Yeon Park ,  Kyoung-Ryul Yoon ,  Dae-Sik Choi ,  Han-Mei Choi ,  Seung-Hwan Lee

    IPC分类号： H01L29/76 ,  H01L29/788 ,  H01L29/792

    CPC分类号： H01L21/022 ,  H01L21/02178 ,  H01L21/02181 ,  H01L21/02189 ,  H01L21/02247 ,  H01L21/0228 ,  H01L21/28273 ,  H01L21/318 ,  H01L29/513 ,  H01L29/7881

    摘要： A semiconductor device and/or gate structure having a composite dielectric layer and methods of manufacturing the same is provided. In the semiconductor device, gate structure, and methods provided, a first conductive layer may be formed on a substrate. A native oxide layer formed on the first conductive layer may be removed. A surface of the first conductive layer may be nitrided so that the surface may be altered into a nitride layer. A composite dielectric layer including the first and/or second dielectric layers may be formed on the nitride layer. A second conductive layer may be formed on the composite dielectric layer. The first dielectric layer may include a material having a higher dielectric constant. The second dielectric layer may be capable of suppressing crystallization of the first dielectric layer.

    摘要翻译： 提供了具有复合电介质层的半导体器件和/或栅极结构及其制造方法。 在半导体器件中，提供栅极结构和方法，可以在衬底上形成第一导电层。 可以除去形成在第一导电层上的自然氧化物层。 第一导电层的表面可以被氮化，使得表面可以改变为氮化物层。 可以在氮化物层上形成包括第一和/或第二电介质层的复合电介质层。 可以在复合介电层上形成第二导电层。 第一电介质层可以包括具有较高介电常数的材料。 第二电介质层可以抑制第一电介质层的结晶化。

    Non-volatile memory device and method of manufacturing the same
    10.
    发明申请
    Non-volatile memory device and method of manufacturing the same 失效
    非易失性存储器件及其制造方法

    公开(公告)号：US20080061360A1

    公开(公告)日：2008-03-13

    申请号：US11898039

    申请日：2007-09-07

    申请人： Se-Hoon Oh ,  Young-Geun Park ,  Han-Mei Choi ,  Seung-Hwan Lee ,  Ki-Yeon Park ,  Sun-Jung Kim

    发明人： Se-Hoon Oh ,  Young-Geun Park ,  Han-Mei Choi ,  Seung-Hwan Lee ,  Ki-Yeon Park ,  Sun-Jung Kim

    IPC分类号： H01L29/792 ,  H01L21/336

    CPC分类号： H01L21/28282 ,  H01L29/4234 ,  H01L29/513 ,  H01L29/792

    摘要： In a non-volatile memory device and a method of manufacturing the non-volatile memory device, a tunnel insulating layer, a charge trapping layer, a dielectric layer and a conductive layer may be sequentially formed on a channel region of a substrate. The conductive layer may be patterned to form a gate electrode and spacers may be formed on sidewalls of the gate electrode. A dielectric layer pattern, a charge trapping layer pattern, and a tunnel insulating layer pattern may be formed on the channel region by an anisotropic etching process using the spacers as an etch mask. Sidewalls of the charge trapping layer pattern may be removed by an isotropic etching process to reduce the width thereof. Thus, the likelihood of lateral diffusion of electrons may be reduced or prevented in the charge trapping layer pattern and high temperature stress characteristics of the non-volatile memory device may be improved.

    摘要翻译： 在非易失性存储器件和制造非易失性存储器件的方法中，隧道绝缘层，电荷俘获层，电介质层和导电层可以顺序形成在衬底的沟道区上。 可以将导电层图案化以形成栅电极，并且可以在栅电极的侧壁上形成间隔物。 可以通过使用间隔物作为蚀刻掩模的各向异性蚀刻工艺在沟道区上形成电介质层图案，电荷俘获层图案和隧道绝缘层图案。 可以通过各向同性蚀刻工艺去除电荷俘获层图案的侧壁以减小其宽度。 因此，电荷捕获层图案中电子的横向扩散的可能性可能会降低或被抑制，并且可以提高非易失性存储器件的高温应力特性。