公开(公告)号：US20120164817A1

公开(公告)日：2012-06-28

申请号：US13411864

申请日：2012-03-05

申请人： Takeshi SHICHI ,  Junichi KOEZUKA ,  Hideto OHNUMA ,  Shunpei YAMAZAKI

发明人： Takeshi SHICHI ,  Junichi KOEZUKA ,  Hideto OHNUMA ,  Shunpei YAMAZAKI

IPC分类号： H01L21/46

CPC分类号： H01L27/1266 ,  H01L21/76254 ,  H01L27/1214 ,  H01L29/66772

摘要： The present invention provides a method for manufacturing an SOI substrate, to improve planarity of a surface of a single crystal semiconductor layer after separation by favorably separating a single crystal semiconductor substrate even in the case where a non-mass-separation type ion irradiation method is used, and to improve planarity of a surface of a single crystal semiconductor layer after separation as well as to improve throughput. The method includes the steps of irradiating a single crystal semiconductor substrate with accelerated ions by an ion doping method while the single crystal semiconductor substrate is cooled to form an embrittled region in the single crystal semiconductor substrate; bonding the single crystal semiconductor substrate and a base substrate with an insulating layer interposed therebetween; and separating the single crystal semiconductor substrate along the embrittled region to form a single crystal semiconductor layer over the base substrate with the insulating layer interposed therebetween.

摘要翻译： 本发明提供一种制造SOI衬底的方法，即使在非质量分离型离子照射方法为非质子分离型离子照射方法的情况下，通过有利地分离单晶半导体衬底来提高分离后的单晶半导体层的表面的平面性 并且在分离之后提高单晶半导体层的表面的平面性以及提高生产量。 该方法包括以下步骤：当单晶半导体衬底被冷却以在单晶半导体衬底中形成脆化区域时，通过离子掺杂方法照射具有加速离子的单晶半导体衬底; 将单晶半导体衬底和基底衬底之间插入绝缘层; 并且沿着脆化区域分离单晶半导体衬底，以在基底衬底上形成绝缘层，形成单晶半导体层。

公开(公告)号：US20110183494A1

公开(公告)日：2011-07-28

申请号：US13011136

申请日：2011-01-21

申请人： Junichi KOEZUKA ,  Hideto OHNUMA

发明人： Junichi KOEZUKA ,  Hideto OHNUMA

IPC分类号： H01L21/762

CPC分类号： H01L21/76254 ,  H01L21/84

摘要： Manufacturing cost of an SOI substrate is reduced. Yield of an SOI substrate is improved. A method for manufacturing an SOI substrate includes the steps of irradiating a single crystal semiconductor substrate with ions to form an embrittled region in the single crystal semiconductor substrate, bonding the single crystal semiconductor substrate to a base substrate with an insulating film therebetween, and separating the single crystal semiconductor substrate and the base substrate at the embrittled region to form a semiconductor layer over the base substrate with the insulating film therebetween. In the step of forming the embrittled region, ion species which are not mass-separated are used as the ions and a temperature of the single crystal semiconductor substrate is set to 250° C. or higher at the time of irradiation with the ions.

摘要翻译： SOI衬底的制造成本降低。 改善了SOI衬底的产量。 一种SOI衬底的制造方法包括以下步骤：在单晶半导体衬底中照射单晶半导体衬底以形成脆化区域，将单晶半导体衬底与绝缘膜之间的绝缘膜接合， 单晶半导体衬底和基底衬底处于脆化区，以在基底衬底上形成半导体层，其间具有绝缘膜。 在形成脆化区域的步骤中，使用未质量分离的离子种类作为离子，并且在照射离子时将单晶半导体基板的温度设定为250℃以上。

公开(公告)号：US20120153395A1

公开(公告)日：2012-06-21

申请号：US13315322

申请日：2011-12-09

申请人： Junichi KOEZUKA ,  Satoshi SHINOHARA ,  Miki SUZUKI ,  Hideto OHNUMA

发明人： Junichi KOEZUKA ,  Satoshi SHINOHARA ,  Miki SUZUKI ,  Hideto OHNUMA

IPC分类号： H01L29/772 ,  H01L21/336

CPC分类号： H01L29/66772 ,  H01L27/1288 ,  H01L29/66492 ,  H01L29/78624

摘要： A semiconductor device is provided, which includes a single crystal semiconductor layer formed over an insulating surface and having a source region, a drain region, and a channel formation region, a gate insulating film covering the single crystal semiconductor layer and a gate electrode overlapping with the channel formation region with the gate insulating film interposed therebetween. In the semiconductor device, at least the drain region of the source and drain regions includes a first impurity region adjacent to the channel formation region and a second impurity region adjacent to the first impurity region. A maximum of an impurity concentration distribution in the first impurity region in a depth direction is closer to the insulating surface than a maximum of an impurity concentration distribution in the second impurity region in a depth direction.

摘要翻译： 提供了一种半导体器件，其包括形成在绝缘表面上并具有源极区，漏极区和沟道形成区的单晶半导体层，覆盖单晶半导体层的栅极绝缘膜和与 沟道形成区域之间插入栅极绝缘膜。 在半导体器件中，源极和漏极区域的至少漏极区域包括与沟道形成区域相邻的第一杂质区域和与第一杂质区域相邻的第二杂质区域。 与深度方向上的第二杂质区域的杂质浓度分布的最大值相比，深度方向上的第一杂质区域的杂质浓度分布的最大值比绝缘面更接近。

公开(公告)号：US20120007095A1

公开(公告)日：2012-01-12

申请号：US13238754

申请日：2011-09-21

申请人： Shunpei YAMAZAKI ,  Satoshi MURAKAMI ,  Jun KOYAMA ,  Yukio TANAKA ,  Hidehito KITAKADO ,  Hideto OHNUMA

发明人： Shunpei YAMAZAKI ,  Satoshi MURAKAMI ,  Jun KOYAMA ,  Yukio TANAKA ,  Hidehito KITAKADO ,  Hideto OHNUMA

IPC分类号： H01L29/38

CPC分类号： G02F1/1368 ,  G02F1/133345 ,  G02F1/13454 ,  G02F1/136227 ,  G02F1/136286 ,  G02F2201/123 ,  G02F2202/104 ,  H01L27/12 ,  H01L27/1222 ,  H01L27/124 ,  H01L27/1248 ,  H01L27/1259 ,  H01L27/3248 ,  H01L27/3258 ,  H01L27/3262 ,  H01L27/3272 ,  H01L27/3276 ,  H01L29/458 ,  H01L29/78621 ,  H01L29/78627 ,  H01L29/78675 ,  H01L2029/7863 ,  H01L2227/323

摘要： This invention provides a semiconductor device having high operation performance and high reliability. An LDD region 707 overlapping with a gate wiring is arranged in an n-channel TFT 802 forming a driving circuit, and a TFT structure highly resistant to hot carrier injection is achieved. LDD regions 717, 718, 719 and 720 not overlapping with a gate wiring are arranged in an n-channel TFT 804 forming a pixel unit. As a result, a TFT structure having a small OFF current value is achieved. In this instance, an element belonging to the Group 15 of the Periodic Table exists in a higher concentration in the LDD region 707 than in the LDD regions 717, 718, 719 and 720.

摘要翻译： 本发明提供一种具有高操作性能和高可靠性的半导体器件。 在形成驱动电路的n沟道TFT 802中配置与栅极配线重叠的LDD区域707，能够实现高耐热载流子注入的TFT结构。 不与栅极布线重叠的LDD区域717,718,719和720被布置在形成像素单元的n沟道TFT 804中。 结果，实现了具有小的截止电流值的TFT结构。 在这种情况下，属于周期表第15族的元素在LDD区707中比在LDD区717,718,719和720中的浓度更高。

公开(公告)号：US20110068339A1

公开(公告)日：2011-03-24

申请号：US12958739

申请日：2010-12-02

申请人： Toshimitsu KONUMA ,  Akira SUGAWARA ,  Yukiko UEHARA ,  Hongyong ZHANG ,  Atsunori SUZUKI ,  Hideto OHNUMA ,  Naoaki YAMAGUCHI ,  Hideomi SUZAWA ,  Hideki UOCHI ,  Yasuhiko TAKEMURA

发明人： Toshimitsu KONUMA ,  Akira SUGAWARA ,  Yukiko UEHARA ,  Hongyong ZHANG ,  Atsunori SUZUKI ,  Hideto OHNUMA ,  Naoaki YAMAGUCHI ,  Hideomi SUZAWA ,  Hideki UOCHI ,  Yasuhiko TAKEMURA

IPC分类号： H01L29/772 ,  H01L27/12

CPC分类号： H01L29/665 ,  H01L21/02145 ,  H01L21/02244 ,  H01L21/02258 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/31683 ,  H01L21/31687 ,  H01L21/321 ,  H01L27/124 ,  H01L27/127 ,  H01L29/458 ,  H01L29/66598 ,  H01L29/66757 ,  H01L29/78621 ,  H01L29/78627

摘要： A TFT formed on an insulating substrate source, drain and channel regions, a gate insulating film formed on at least the channel region and a gate electrode formed on the gate insulating film. Between the channel region and the drain region, a region having a higher resistivity is provided in order to reduce an Ioff current. A method for forming this structure comprises the steps of anodizing the gate electrode to form a porous anodic oxide film on the side of the gate electrode; removing a portion of the gate insulating using the porous anodic oxide film as a mask so that the gate insulating film extends beyond the gate electrode but does not completely cover the source and drain regions. Thereafter, an ion doping of one conductivity element is performed. The high resistivity region is defined under the gate insulating film.

摘要翻译： 形成在绝缘基板源极，漏极和沟道区上的TFT，至少形成在沟道区上的栅极绝缘膜和形成在栅极绝缘膜上的栅电极。 在沟道区域和漏极区域之间，提供具有较高电阻率的区域以便减小偏转电流。 形成该结构的方法包括以下步骤：在栅电极侧阳极氧化栅电极以形成多孔阳极氧化膜; 使用多孔阳极氧化膜去除一部分栅极绝缘体作为掩模，使得栅极绝缘膜延伸超过栅极电极但不完全覆盖源极和漏极区域。 此后，进行一个导电性元素的离子掺杂。 高电阻率区域限定在栅极绝缘膜下。

公开(公告)号：US20100244051A1

公开(公告)日：2010-09-30

申请号：US12731699

申请日：2010-03-25

申请人： Hideto OHNUMA

发明人： Hideto OHNUMA

IPC分类号： H01L29/24 ,  H01L21/18

CPC分类号： H01L29/66068 ,  H01L21/76254 ,  H01L21/8213 ,  H01L21/84 ,  H01L27/12 ,  H01L29/1608 ,  H01L29/66651 ,  H01L29/66772 ,  H01L29/78684

摘要： An object is to realize an integrated circuit included in a semiconductor device which has multiple functions, or to increase the size of an integrated circuit even when the integrated circuit is formed using a silicon carbide substrate. The integrated circuit includes a first transistor including an island-shaped silicon carbide layer provided over a substrate with a first insulating layer interposed therebetween, a first gate insulating layer provided over the silicon carbide layer, and a first conductive layer provided over the first gate insulating layer and overlapped with the silicon carbide layer; and a second transistor including an island-shaped single crystal silicon layer provided over the substrate with a second insulating layer interposed therebetween, a second gate insulating layer provided over the single crystal silicon layer, and a second conductive layer provided over the second gate insulating layer and overlapped with the single crystal silicon layer.

摘要翻译： 本发明的目的是实现具有多种功能的半导体器件中的集成电路，或者即使当使用碳化硅衬底形成集成电路时也可以增加集成电路的尺寸。 集成电路包括：第一晶体管，包括设置在基板上的岛状碳化硅层，其间插入有第一绝缘层，设置在碳化硅层上的第一栅极绝缘层，以及设置在第一栅极绝缘层上的第一导电层 并与碳化硅层重叠; 以及第二晶体管，其包括设置在所述基板上的岛状单晶硅层，其间插入有第二绝缘层，设置在所述单晶硅层上的第二栅极绝缘层，以及设置在所述第二栅极绝缘层上的第二导电层 并与单晶硅层重叠。

公开(公告)号：US20100096720A1

公开(公告)日：2010-04-22

申请号：US12580532

申请日：2009-10-16

申请人： Hideto OHNUMA ,  Eiji HIGA

发明人： Hideto OHNUMA ,  Eiji HIGA

IPC分类号： H01L29/06 ,  H01L21/762

CPC分类号： H01L21/76254

摘要： To provide an SOI substrate having a high mechanical strength, and a method for manufacturing the SOI substrate, a single crystal semiconductor substrate is irradiated with accelerated ions so that an embrittled region is formed in a region at a predetermined depth from a surface of the single crystal semiconductor substrate; the single crystal semiconductor substrate is bonded to a base substrate with an insulating layer interposed therebetween; the single crystal semiconductor substrate is heated to be separated along the embrittled region, so that a semiconductor layer is provided over the base substrate with the insulating layer interposed therebetween; and a surface of the semiconductor layer is irradiated with a laser beam so that at least a superficial part of the semiconductor layer is melted, whereby at least one of nitrogen, oxygen, and carbon is solid-dissolved in the semiconductor layer.

摘要翻译： 为了提供具有高机械强度的SOI衬底以及SOI衬底的制造方法，用加速离子照射单晶半导体衬底，使得在距离单个表面的表面预定深度的区域中形成脆化区域 晶体半导体衬底; 将单晶半导体基板与绝缘层接合在基底基板上， 单晶半导体衬底被加热以沿着脆化区域分离，从而在绝缘层之间设置在基底衬底上的半导体层; 并且用激光束照射半导体层的表面，使得至少半导体层的表面部分熔化，由此氮，氧和碳中的至少一个固体溶解在半导体层中。

公开(公告)号：US20090263942A1

公开(公告)日：2009-10-22

申请号：US12420887

申请日：2009-04-09

申请人： Hideto OHNUMA ,  Noritsugu NOMURA

发明人： Hideto OHNUMA ,  Noritsugu NOMURA

IPC分类号： H01L21/336

CPC分类号： H01L21/76254 ,  H01L21/84 ,  H01L27/1233 ,  H01L29/78621

摘要： A single crystal semiconductor substrate including an embrittlement layer is attached to a base substrate with an insulating layer interposed therebetween, and the single crystal semiconductor layer is separated at the embrittlement layer by heat treatment; accordingly, a single crystal semiconductor layer is fixed over the base substrate. The single crystal semiconductor layer is irradiated with a laser beam so that the single crystal semiconductor layer is partially melted and then is re-single crystallized, whereby crystal defects are removed. In addition, an island-shaped single crystal semiconductor layer for forming an n-channel transistor is channel-doped using a photomask and then is etched back using the photomask so that the island-shaped single crystal semiconductor layer for forming an n-channel transistor is thinner than the island-shaped single crystal semiconductor layer for forming a p-channel transistor.

摘要翻译： 将具有脆化层的单晶半导体基板安装在基板上，其间插入有绝缘层，并且通过热处理在脆化层处分离单晶半导体层; 因此，单晶半导体层固定在基底基板上。 用激光束照射单晶半导体层，使得单晶半导体层部分熔融，然后重新单晶化，从而除去晶体缺陷。 此外，用于形成n沟道晶体管的岛状单晶半导体层使用光掩模进行沟道掺杂，然后使用光掩模进行回蚀，从而形成用于形成n沟道晶体管的岛状单晶半导体层 比用于形成p沟道晶体管的岛状单晶半导体层薄。

公开(公告)号：US20090223628A1

公开(公告)日：2009-09-10

申请号：US12366728

申请日：2009-02-06

申请人： Hideto OHNUMA ,  Tomoaki MORIWAKA

发明人： Hideto OHNUMA ,  Tomoaki MORIWAKA

IPC分类号： B32B37/00

CPC分类号： B32B37/025 ,  B32B38/0012 ,  B32B38/162 ,  B32B2309/02 ,  B32B2309/08 ,  B32B2309/105 ,  B32B2309/72 ,  B32B2310/028 ,  B32B2310/0409 ,  B32B2457/14 ,  B32B2457/20 ,  B32B2457/202 ,  H01L21/67046 ,  H01L21/67092 ,  H01L21/67766

摘要： A method for bonding a plurality of single crystal semiconductor substrates to a large supporting substrate such as a glass substrate while effectively aligning the substrates, and a method for reducing contaminants attached to a bonding surface during the bonding process. A plurality of single crystal semiconductor substrates are arranged on corresponding trays so that the front surfaces of the substrates face vertically downward, and a large supporting substrate is arranged so that the front surface thereof faces vertically upward. Next, the single crystal semiconductor substrates are spaced from the trays, and pressure is applied to part of each of the single crystal semiconductor substrates while the edges thereof are supported, whereby the front surfaces of the single crystal semiconductor substrates are bonded to the front surface of the large supporting substrate.

摘要翻译： 一种用于将多个单晶半导体衬底接合到诸如玻璃衬底的大支撑衬底同时有效地对准衬底的方法，以及用于在接合工艺期间减少附着到接合表面的污染物的方法。 多个单晶半导体基板被布置在相应的托盘上，使得基板的前表面垂直向下，并且大的支撑基板被布置成使得其前表面垂直向上。 接下来，单晶半导体基板与托盘间隔开，并且在其每个单晶半导体基板的一部分被支撑的同时施加到每个单晶半导体基板的一部分，由此单晶半导体基板的前表面被接合到前表面 的大支撑基板。

公开(公告)号：US20070001225A1

公开(公告)日：2007-01-04

申请号：US11425545

申请日：2006-06-21

申请人： Hideto OHNUMA ,  Shigeharu MONOE

发明人： Hideto OHNUMA ,  Shigeharu MONOE

IPC分类号： H01L21/84 ,  H01L27/12

CPC分类号： H01L27/1214 ,  H01L27/124 ,  H01L27/127 ,  H01L27/1288 ,  H01L29/78624

摘要： To provide a manufacturing method in which LDD regions with different widths are formed in a self-aligned manner, and the respective widths are precisely controlled in accordance with each circuit. By using a photomask or a reticle provided with an auxiliary pattern having a light intensity reduction function formed of a diffraction grating pattern or a semi-transparent film, the width of a region with a small thickness of a gate electrode can be freely set, and the widths of two LDD regions capable of being formed in a self-aligned manner with the gate electrode as a mask can be different in accordance with each circuit. In one TFT, both of two LDD regions with different widths overlap a gate electrode.

摘要翻译： 为了提供以自对准方式形成具有不同宽度的LDD区域的制造方法，并且根据每个电路精确地控制各个宽度。 通过使用具有由衍射光栅图案或半透明膜形成的具有光强度降低功能的辅助图案的光掩模或掩模版，可以自由地设定栅电极厚度的区域的宽度，并且 能够以与栅电极为掩模的自对准方式形成的两个LDD区域的宽度可以根据每个电路而不同。 在一个TFT中，具有不同宽度的两个LDD区域都与栅电极重叠。